Publications by Jinhwan Jeon
International Journals
- Jinhwan Jeon and Kiyoung Choi, “Effective synthesis algorithm for partitioned bus architecture,” Electronics Letters, vol. 35, no. 6, Mar. 1999.
International Conferences
- Daehong Kim, Jinyong Jung, Sunghyun Lee, Jinhwan Jeon, and Kiyoung Choi, “Behavior-to-placed RTL synthesis with performance-driven placement,” International Conference on Computer-Aided Design, Nov. 2001.
- Jinhwan Jeon, Daehong Kim, Dongwan Shin, and Kiyoung Choi, “High-level synthesis under multi-cycle interconnect delay,” Asia and South Pacific Design Automation Conference, pp. 662-667, Jan. 2001.
- Junghwan Choi, Jinhwan Jeon, and Kiyoung Choi, “Power minimization of functional units by partially guarded computation,” International Symposium on Low Power Electronics and Design, pp. 131-136, Jul. 2000.
- Sanghun Park, Kihun Kim, Hyunseok Chang, Jinhwan Jeon, and Kiyoung Choi, “Backward-annotation of post-layout delay information into high-level synthesis process for performance optimization,” International Conference of VLSI and CAD, pp. 25-28, Oct. 1999.
- Jinhwan Jeon and Kiyoung Choi, “Loop pipelining in hardware-software partitioning,” Asia and South Pacific Design Automation Conference, pp. 361-366, Feb. 1998.
- Sungjoo Yoo, Jinhwan Jeon, Seongsoo Hong, and Kiyoung Choi, “Hardware-Software codesign of resource-constrained real-time systems,” International Conference on Real-Time and Embedded Computing Systems and Applications, pp. 286-292, Oct. 1996.
Domestic Journals
- 전진환, 최기영, “새로운 시뮬레이티드 어닐링 알고리즘을 이용한 회로 분할 방법”, 전자공학회논문지, vol. 33, no. 9, pp. 223-232, 1996.
Domestic Conferences
- 최정환, 전진환, 최기영, “입력 데이터의 부분적 차단을 통한 저전력 기능유닛의 합성”, 한국반도체 학술대회 논문집, pp. 267-268, 2000. 1.
- 김형섭, 안태균, 전진환, 김대홍, 최기영, “입력데이터의 상관관계를 고려한 기능 유닛 소비 전력 예측”, 한국반도체 학술대회 논문집, pp. 417-418, 1999. 2.
- 전진환, 최기영, “새로운 시뮬레이티드 어닐링 알고리즘을 이용한 회로 분할 방법”, 대한전자공학회 학술회의, pp. 1089-1092, 1995. 12.