Publications by Sungjoo Yoo

International Journals

  1. Jinho Lee, Heesu Kim, Sungjoo Yoo, Kiyoung Choi, H. Peter Hofstee, Gi-Joon Nam, Mark R. Nutter, and Damir Jamsek, “ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator,” Proceedings of the VLDB Endowment, vol. 10, no. 12, pp. 1706-1717, Aug. 2017.
  2. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “AIM: Energy-efficient aggregation inside the memory hierarchy,” ACM Transactions on Architecture and Code Optimization, vol. 13, no. 4, pp. 34:1-34:24, Oct. 2016.
  3. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “Prediction hybrid cache: An energy-efficient STT-RAM cache architecture,” IEEE Transactions on Computers, vol. 65, no. 3, pp. 940-951, Mar. 2016.
  4. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “Low-power hybrid memory cubes with link power management and two-level prefetching,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 2, pp. 453-464, Feb. 2016.
  5. Junhee Yoo, Sungjoo Yoo, and Kiyoung Choi, “Active memory processor for network-on-chip-based architecture,” IEEE Transactions on Computers, vol. 61, no. 5, pp. 622-635, May 2012.
  6. Junhee Yoo, Sungjoo Yoo, and Kiyoung Choi, “Topology/floorplan/pipeline co-design of cascaded bus,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 8, pp. 1034-1047, Aug. 2009.
  7. Jinyong Jung, Sungjoo Yoo, and Kiyoung Choi, “Fast cycle-approximate MPSoC simulation based on synchronization time-point prediction,” Design Automation for Embedded Systems, vol. 11, no. 4, pp. 223-247, Dec. 2007.
  8. Yongjin Ahn, Daehong Kim, Sunghyun Lee, Sanggyu Park, Sungjoo Yoo, Kiyoung Choi, and Soo-Ik Chae, “An efficient simulation environment and simulation techniques for Bluetooth device design,” Design Automation for Embedded Systems, vol. 8, no. 2-3, pp. 119-138, Sep. 2003.
  9. Sungjoo Yoo, Kiyoung Choi, and Dong Sam Ha, “Performance improvement of geographically distributed cosimulation by hierarchically grouped messages,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 5, Oct. 2000.
  10. Sungjoo Yoo and Kiyoung Choi, “Optimizing timed cosimulation by hybrid synchronization,” Design Automation for Embedded Systems, vol. 5, no. 2, Jun. 2000.

International Conferences

  1. Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, “A scalable processing-in-memory accelerator for parallel graph processing,” International Symposium on Computer Architecture, pp. 105-117, Jun. 2015.
  2. Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, “PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture,” International Symposium on Computer Architecture, pp. 336-348, Jun. 2015.
  3. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “Dynamic power management of off-chip links for hybrid memory cubes,” Design Automation Conference, pp. 139:1-139:6, Jun. 2014.
  4. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “DASCA: dead write prediction assisted STT-RAM cache architecture,” International Symposium on High Performance Computer Architecture, pp. 25-36, Feb. 2014.
  5. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “Write intensity prediction for energy-efficient non-volatile caches,” International Symposium on Low Power Electronics and Design, pp. 223-228, Sep. 2013.
  6. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches,” Asia and South Pacific Design Automation Conference, pp. 285-290, Jan. 2013.
  7. Junhee Yoo, Sungjoo Yoo, and Kiyoung Choi, “Multiprocessor system-on-chip designs with active memory processors for higher memory efficiency,” Design Automation Conference, pp. 806-811, Jul. 2009.
  8. Dongwook Lee, Sungjoo Yoo, and Kiyoung Choi, “Entry control in network-on-chip for memory power reduction,” International Symposium on Low Power Electronics and Design, pp. 171-176, Aug. 2008.
  9. Junhee Yoo, Dongwook Lee, Sungjoo Yoo, and Kiyoung Choi, “Communication architecture synthesis of cascaded bus matrix,” Asia and South Pacific Design Automation Conference, pp. 171-177, Jan. 2007.
  10. Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, and Ahmed Amine Jerraya, “Scheduler implementation in MPSoC design,” Asia and South Pacific Design Automation Conference, pp. 151-156, Jan. 2005.
  11. Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, and Nacer-Eddine Zergainoh, “Scheduling and timing analysis of HW/SW On-chip communication in MP SoC design,” DATE Conference and Exhibition, pp. 132-137, Mar. 2003.
  12. Sunghyun Lee, Sungjoo Yoo, and Kiyoung Choi, “An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model,” International Symposium on Low Power Electronics and Design, pp. 84-87, Aug. 2002.
  13. Sunghyun Lee, Sungjoo Yoo, and Kiyoung Choi, “Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model,” International Symposium on Hardware/Software Codesign, pp. 199-204, May 2002.
  14. Yongjin Ahn, Daehong Kim, Sunghyun Lee, Sanggyu Park, Sungjoo Yoo, Kiyoung Choi, and Soo-Ik Chae, “An efficient simulation environment for the design of networked Bluetooth devices,” Design, Automation and Test in Europe, Mar. 2002.
  15. Jinyong Jung, Sungjoo Yoo, and Kiyoung Choi, “Performance improvement of multi-processor systems cosimulation based on SW analysis,” DATE Conference and Exhibition, pp. 749-753, Mar. 2001.
  16. Sungjoo Yoo, Kyoungseok Rha, Youngchul Cho, Jinyong Jung, and Kiyoung Choi, “Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model,” International Workshop on Hardware/Software Codesign, pp. 77-81, May 2000.
  17. Sungjoo Yoo, Jongeun Lee, Jinyong Jung, Kyoungseok Rha, Youngchul Cho, and Kiyoung Choi, “Fast hardware-software coverification by optimistic execution of real processor,” DATE Conference and Exhibition, pp. 663-668, Mar. 2000.
  18. Byungil Jeong, Sungjoo Yoo, Sunghyun Lee, and Kiyoung Choi, “Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs,” Asia and South Pacific Design Automation Conference, pp. 169-174, Jan. 2000.
  19. Sungjoo Yoo, Jongeun Lee, Kyoungseok Rha, Jinyong Jung, Youngchul Cho, and Kiyoung Choi, “Fast prototyping of an IS-95 CDMA cellular phone : a case study,” Asia Pacific Conference on Hardware Description Languages, pp. 61-66, Oct. 1999.
  20. Sungjoo Yoo and Kiyoung Choi, “Interleaving partial bus-invert coding for low power reconfiguration of FPGAs,” International Conference on VLSI and CAD, pp. 549-552, Oct. 1999.
  21. Sungjoo Yoo and Kiyoung Choi, “Optimizing geographically distributed timed cosimulation by hierarchically grouped messages,” International Workshop on Hardware/Software Codesign, pp. 100-104, May 1999.
  22. Byungil Jeong, Sungjoo Yoo, and Kiyoung Choi, “Exploiting early partial reconfiguration of run-time reconfigurable FPGAs in embedded systems design,” International Symposium on Field Programmable Gate Arrays, pp. 247-247, Feb. 1999.
  23. Sungjoo Yoo and Kiyoung Choi, “Optimistic distributed timed cosimulation based on thread simulation model,” International Workshop on Hardware/Software Codesign, pp. 71-75, 1998.
  24. Sungjoo Yoo and Kiyoung Choi, “Optmistic timed HW-SW cosimulation,” Asia Pacific Conference on Hardware Description Languages, pp. 39-42, 1997.
  25. Sungjoo Yoo and Kiyoung Choi, “Synchronization overhead reduction in timed cosimulation,” International High Level Design Validation and Test Workshop, pp. 157-164, 1997.
  26. Sungjoo Yoo, Jinhwan Jeon, Seongsoo Hong, and Kiyoung Choi, “Hardware-Software codesign of resource-constrained real-time systems,” International Conference on Real-Time and Embedded Computing Systems and Applications, pp. 286-292, Oct. 1996.
  27. Sungjoo Yoo and Kiyoung Choi, “High performance FPGA interconnect delay estimation,” Flat Panel Display Conference, 1996.

International Books

  1. Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, and Nacer-Eddine Zergainoh, “Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design,” in Embedded Software for SoC, Ahmed Amine Jerraya, Sungjoo Yoo, Diederik Verkest, and Nobert Wehn, eds., Kluwer Academic Publishers, pp. 125-136, Dec. 2003.

Domestic Journals

  1. 안준환, 유승주, 최기영, “프로세싱 인 메모리 시스템”, 정보과학회지, vol. 34, no. 7, pp. 15-22, 2016. 7.
  2. 이성현, 유승주, 최기영, “Hierarchical FSM과 synchronous dataflow model을 이용한 재구성 가능한 SoC의 설계”, 전자공학회논문지, vol. 40, no. 8, pp. 77-88, 2003. 8.
  3. 유승주, 최기영, “RC tree의 지연시간 예측”, 전자공학회논문지, vol. 32A, no. 12, pp. 209-219, 1995.

Domestic Conferences

  1. 안용진, 김대홍, 이성현, 박상규, 유승주, 최기영, 채수익, “An efficient simulation environment for the design of networked bluetooth devices”, SoC Design Conference, pp. 622-628, 2001. 11.
  2. 정진용, 유승주, 최기영, “Performance improvement of multi-processor systems cosimulation based on SW”, CAD 및 VLSI 설계 연구회 학술 발표회 논문집, pp. 159-163, 2001. 5.
  3. 이성현, 유승주, 최기영, “Java 기반의 재구성 가능한 내장형 시스템 architecture 및 개발환경”, 한국반도체 학술대회 논문집, pp. 495-496, 2000. 1.
  4. 정병일, 유승주, 최기영, “재구성 가능한 아키텍처를 위한 HW/SW 분할 및 스케줄링”, 한국반도체 학술대회 논문집, pp. 539-540, 1999. 2.

Domestic Patents

  1. 최기영, 유준희, 유승주, 신현철, “능동 메모리 프로세서를 포함하는 네트워크-온-칩 시스템”, 한국, 한양대학교 산학협력단, 서울대학교 산학협력단, 2000-00-00, 1010397820000, 2011-06-01.
  2. 김현철, 최기영, 유승주, 이종은, 정진용, 나경석, 조영철, “실제 프로세서를 이용한 낙관적 실행에 의한 하드웨어-소프트웨어 통합 검증방법”, 한국, 한국 MDS (주), 2000-01-18, 2000-002175, 2003-01-06, 368546.