Publications by Kiyoung Choi

International Journals

  1. Aidyn Zhakatayev, Kyounghoon Kim, Kiyoung Choi, and Jongeun Lee, “An efficient and accurate stochastic number generator using even-distribution coding,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 12, pp. 3056-3066, Dec. 2018.
  2. Namhyung Kim, Junwhan Ahn, Kiyoung Choi, Daniel Sanchez, Donghoon Yoo, and Soojung Ryu, “Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems,” ACM Transactions on Architecture and Code Optimization, vol. 15, no. 1, pp. 10:1-10:23, Mar. 2018.
  3. Jongho Kim, Kiyoung Choi, Yonghwan Kim, Wook Kim, Kyungtae Do, and Jungyun Choi, “Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 1, pp. 37-49, Jan. 2018.
  4. Mansureh S. Moghaddam, Kiyoung Choi and M. Balakrishnan, “Optimal Mapping of Program Overlays onto Many-Core Platforms with Limited Mmory Capacity,” Design Automation for Embedded Systems, vol. 21, no. 3-4, pp. 173-194, Dec. 2017.
  5. Hyunjik Song and Kiyoung Choi, “Autonomic diffusive load balancing on many-core architecture using simulated annealing,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E100-A, no. 8, pp. 1640-1649, Aug. 2017.
  6. Jinho Lee, Heesu Kim, Sungjoo Yoo, Kiyoung Choi, H. Peter Hofstee, Gi-Joon Nam, Mark R. Nutter, and Damir Jamsek, “ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator,” Proceedings of the VLDB Endowment, vol. 10, no. 12, pp. 1706-1717, Aug. 2017.
  7. Jinho Lee, Jongwook Chung, Jung Ho Ahn, and Kiyoung Choi, “Excavating the hidden parallelism inside DRAM architectures with buffered compares,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 6, pp. 1793-1806, Jun. 2017.
  8. Dongwoo Lee, Sangheon Lee, Soojung Ryu, and Kiyoung Choi, “Dirty-Block Tracking in a Direct-Mapped DRAM Cache with Self-Balancing Dispatch,” ACM Transactions on Architecture and Code Optimization, vol. 14, no. 2, pp. 11:1-11:25, May. 2017.
  9. Namhyung Kim and Kiyoung Choi, “Exploration of trade-offs in the design of volatile STT-RAM cache,” Journal of Systems Architecture, vol. 71, pp. 23-31, Nov. 2016.
  10. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “AIM: Energy-efficient aggregation inside the memory hierarchy,” ACM Transactions on Architecture and Code Optimization, vol. 13, no. 4, pp. 34:1-34:24, Oct. 2016.
  11. Kyounghoon Kim, Helin Lin, Jinyoung Choi, and Kiyoung Choi, “A design framework for hierarchical ensemble of multiple feature extractors and multiple classifiers,” Pattern Recognition, vol. 52, pp. 1-16, Apr. 2016.
  12. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “Prediction hybrid cache: An energy-efficient STT-RAM cache architecture,” IEEE Transactions on Computers, vol. 65, no. 3, pp. 940-951, Mar. 2016.
  13. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “Low-power hybrid memory cubes with link power management and two-level prefetching,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 2, pp. 453-464, Feb. 2016.
  14. Hanmin Park and Kiyoung Choi, “Adaptively weighted round-robin arbitration for equality of service in a many-core network-on-chip,” IET Computers & Digital Techniques, vol. 10, no. 1, pp. 37-44, Jan. 2016.
  15. Jinho Lee, Kyungsu Kang, and Kiyoung Choi, “REDELF: An energy-efficient deadlock-free routing for 3D NoCs with partial vertical connections,” ACM Journal on Emerging Technologies in Computing Systems, vol. 12, no. 3, pp. 26:1-26:22, Jan. 2015.
  16. Kyuseung Han, Ganghee Lee, and Kiyoung Choi, “Software-level approaches for tolerating transient faults in a coarse-grained reconfigurable architecture,” IEEE Transactions on Dependable and Secure Computing, vol. 11, no. 4, pp. 392-398, Jul. 2014.
  17. Junwhan Ahn and Kiyoung Choi, “LASIC: loop-aware sleepy instruction caches based on STT-RAM technology,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp. 1197-1201, May 2014.
  18. Jongeun Lee, Seongseok Seo, Jong Kyung Paek, and Kiyoung Choi, “Configurable range memory for effective data reuse on programmable accelerators,” ACM Transactions on Design Automation of Electronic Systems, vol. 19, no. 2, pp. 13:1-13:22, Mar. 2014.
  19. Seokhyun Lee and Kiyoung Choi, “Critical-path-aware high-level synthesis with distributed controller for fast timing closure,” ACM Transactions on Design Automation of Electronic Systems, vol. 19, no. 2, pp. 16:1-16:29, Mar. 2014.
  20. Manhwee Jo, Dongwook Lee, Kyuseung Han, and Kiyoung Choi, “Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study,” Integration, the VLSI Journal, vol. 47, no. 2, pp. 232-241, Mar. 2014.
  21. Jinho Lee, Moo-Kyoung Chung, Yeon-Gon Cho, Soojung Ryu, Jung Ho Ahn, and Kiyoung Choi, “Mapping and scheduling of tasks and communications on many-core SoC under local memory constraint,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 11, pp. 1748-1761, Nov. 2013.
  22. Jinho Lee, Dongwoo Lee, Sunwook Kim, and Kiyoung Choi, “Deflection routing in 3D network-on-chip with limited vertical bandwidth,” ACM Transactions on Design Automation of Electronic Systems, vol. 18, no. 4, pp. 50:1-50:22, Oct. 2013.
  23. Kyuseung Han, Junwhan Ahn, and Kiyoung Choi, “Power-efficient predication techniques for acceleration of control flow execution on CGRA,” ACM Transactions on Architecture and Code Optimization, vol. 10, no. 2, pp. 8:1-8:25, May 2013.
  24. Junwhan Ahn and Kiyoung Choi, “Isomorphism-aware identification of custom instructions with I/O serialization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 1, pp. 34-46, Jan. 2013.
  25. Rohit Sharma, Tapas Chakravarty, and Kiyoung Choi, “Fast and efficient extraction algorithm for high-speed interconnects with arbitrary boundaries,” Journal of Supercomputing, vol. 62, no. 1, pp. 251-264, Oct. 2012.
  26. John Kim, Kiyoung Choi, and Gabriel Loh, “Exploiting new interconnect technologies in on-chip communication,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 2, no. 2, pp. 124-136, Jun. 2012.
  27. Junhee Yoo, Sungjoo Yoo, and Kiyoung Choi, “Active memory processor for network-on-chip-based architecture,” IEEE Transactions on Computers, vol. 61, no. 5, pp. 622-635, May 2012.
  28. Ganghee Lee, Kiyoung Choi, and Nikil D. Dutt, “Mapping multi-domain applications onto coarse-grained reconfigurable architectures,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 5, pp. 637-650, May 2011.
  29. Di Wu, Imyong Lee, Junwhan Ahn, and Kiyoung Choi, “Fast generation of multiple custom instructions under area constraints,” Journal of Semiconductor Technology and Science, vol. 11, no. 1, pp. 51-58, Mar. 2011.
  30. Kiyoung Choi, “Coarse-grained reconfigurable array: architecture and application mapping”, IPSJ Transactions on System LSI Design Methodology, vol. 4, no. pp. 31-46, Feb. 2011.
  31. Yoonjin Kim, Rabi N. Mahapatra, and Kiyoung Choi, “Design space exploration for efficient resource utilization in coarse-grained reconfigurable architecture,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 10, pp. 1471-1482, Oct. 2010.
  32. Jong Kyung Paek, Kiyoung Choi, and Jongeun Lee, “Binary acceleration using coarse-grained reconfigurable architecture,” ACM SIGARCH Computer Architecture News, vol. 38, no. 4, pp. 33-39, Sep. 2010.
  33. Ganghee Lee, Yongjin Ahn, Seokhyun Lee, Jeongki Son, Kiwook Yun, and Kiyoung Choi, “Communication architecture design for reconfigurable multimedia SoC platform,” Design Automation for Embedded Systems, vol. 14, no. 1, pp. 1-20, Mar. 2010.
  34. Kyuseung Han and Kiyoung Choi, “Library-based mapping of application to reconfigurable array architecture,” Journal of Semiconductor Technology and Science, vol. 9, no. 4, pp. 209-215, Dec. 2009.
  35. Junhee Yoo, Sungjoo Yoo, and Kiyoung Choi, “Topology/floorplan/pipeline co-design of cascaded bus,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 8, pp. 1034-1047, Aug. 2009.
  36. Yoonjin Kim, Rabi N. Mahapatra, Ilhyun Park, and Kiyoung Choi, “Low power reconfiguration technique for coarse-grained reconfigurable architecture,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 5, pp. 593-603, May 2009.
  37. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “Evaluating memory architectures for media applications on coarse-grained reconfigurable architectures,” International Journal of Embedded Systems, vol. 3, no. 3, pp. 119-127, Oct. 2008.
  38. Yongjin Ahn, Keesung Han, Ganghee Lee, Hyunjik Song, Junhee Yoo, Kiyoung Choi, and Xingguang Feng, “SoCDAL: System-on-Chip Design AcceLerator,” ACM Transactions on Design Automation of Electronic Systems, vol. 17, no. 1, pp. 1-38, Jan. 2008.
  39. Jinyong Jung, Sungjoo Yoo, and Kiyoung Choi, “Fast cycle-approximate MPSoC simulation based on synchronization time-point prediction,” Design Automation for Embedded Systems, vol. 11, no. 4, pp. 223-247, Dec. 2007.
  40. Youngchul Cho and Kiyoung Choi, “Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip,” Design Automation for Embedded Systems, vol. 11, no. 2-3, pp. 167-191, Jul. 2007.
  41. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “Instruction set synthesis with efficient instruction encoding for configurable processors,” ACM Transactions on Design Automation of Electronic Systems, vol. 12, no. 1, pp. 1-37, Jan. 2007.
  42. Daehong Kim, Dongwan Shin, and Kiyoung Choi, “Pipelining with common operands for power-efficient linear systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 9, pp. 1023-1034, Sep. 2005.
  43. Yongjin Ahn, Daehong Kim, Sunghyun Lee, Sanggyu Park, Sungjoo Yoo, Kiyoung Choi, and Soo-Ik Chae, “An efficient simulation environment and simulation techniques for Bluetooth device design,” Design Automation for Embedded Systems, vol. 8, no. 2-3, pp. 119-138, Sep. 2003.
  44. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “An algorithm for mapping loops onto coarse-grained reconfigurable architectures,” ACM SIGPLAN Notices, vol. 38, no. 7, pp. 183-188, Jul. 2003.
  45. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “Compilation approach for coarse-grained reconfigurable architectures,” IEEE Design & Test of Computers, vol. 20, no. 1, pp. 26-33, Jan. 2003.
  46. Nikil D. Dutt and Kiyoung Choi, “Configurable processors for embedded computing,” IEEE Computer, vol. 36, no. 1, pp. 120-123, Jan. 2003.
  47. Youngsoo Shin, Kiyoung Choi, and Takayasu Sakurai, “Power-conscious scheduling for real-time embedded systems design,” VLSI Design, vol. 12, no. 2, Dec. 2001.
  48. Youngsoo Shin, Kiyoung Choi, and Young-Hoon Chang, “Narrow bus encoding for low-power DSP systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 5, Oct. 2001.
  49. Youngsoo Shin, Kiyoung Choi, and Soo-Ik Chae, “Partial bus-invert coding for power optimization of application-specific system,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 2, Apr. 2001.
  50. Sanghun Park and Kiyoung Choi, “Performance-driven high-level synthesis with bit-level chaining and clock selection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, Feb. 2001.
  51. Sungjoo Yoo, Kiyoung Choi, and Dong Sam Ha, “Performance improvement of geographically distributed cosimulation by hierarchically grouped messages,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 5, Oct. 2000.
  52. Sungjoo Yoo and Kiyoung Choi, “Optimizing timed cosimulation by hybrid synchronization,” Design Automation for Embedded Systems, vol. 5, no. 2, Jun. 2000.
  53. Jinhwan Jeon and Kiyoung Choi, “Effective synthesis algorithm for partitioned bus architecture,” Electronics Letters, vol. 35, no. 6, Mar. 1999.
  54. Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, and Kiyoung Choi, “An integrated cosimulation environment for heterogeneous systems prototyping,” Design Automation for Embedded Systems, vol. 3, no. 2-3, May 1998.
  55. Sanghun Park and Kiyoung Choi, “Latency minimisation by system clock optimisation,” Electronics Letters, vol. 34, no. 9, pp. 862-864, Jan. 1998.
  56. Youngsoo Shin, Soo-Ik Chae, and Kiyoung Choi, “Reduction of bus transitions with partial bus-invert coding,” Electronics Letters, vol. 34, no. 7, pp. 642-643, 1998.
  57. Taekyoon Ahn and Kiyoung Choi, “Dynamic operand interchange for low power,” Electronics Letters, vol. 33, no. 25, pp. 2118-2120, Jan. 1997.
  58. KiJong Lee and Kiyoung Choi, “Self-timed divider based on RSD number system,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, no. 2, pp. 292-295, Jan. 1996.
  59. Yongjoo Kim, Kyuseok Kim, and Kiyoung Choi, “Efficient VLSI architecture for lossless data compression,” Electronics Letters, vol. 31, no. 13, pp. 1053-1054, Jan. 1995.
  60. Kiyoung Choi, KiJong Lee, and Jun-Woo Kang, “Self-timed divider using the redundant signed digit number system,” International Journal of Electronics, vol. 79, no. 2, pp. 183-192, Jan. 1995.

International Conferences

  1. Chaeun Lee, Jaehyun Kim, and Kiyoung Choi, “An RRAM-based Analog Neuron Design for the Weighted Spiking Neural Netwworks,” International SoC Design Conference, Oct. 2019 (accepted).
  2. Chaeun Lee, Jaehyun Kim, Jihun Kim, Jaehyun Kim, and Kiyoung Choi, “Fast Simulation Method for Analog Deep Binarized Neural Networks,” International SoC Design Conference, Oct. 2019 (accepted).
  3. Jaehyun Kim†, Chaeun Lee†, Jihun Kim, Yumin Kim, and Kiyoung Choi, “VCAM: Variation Compensation through Activation Matching for Analog Binarized Neural Networks,” International Symposium on Low Power Electronics and Design, July, 2019 († indicates equal contribution).
  4. Gunhee Lee, Hanmin Park, Namhyung Kim, Joonsang Yu, Sujeong Jo, and Kiyoung Choi, “Acceleration of DNN Backward Propagation by Selective Computation of Gradients,” In Proceedings of the 56th Annual Design Automation Conference 2019 (DAC ‘19), June. 2019.
  5. Jongho Kim, Heesu Kim, H. Amrouch, J. Henkel, A. Gerstlauer and Kiyoung Choi, “Aging Gracefully with Approximation,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), May. 2019.
  6. Joonsang Yu, Sungbum Kang, and Kiyoung Choi, “Network Recasting: A Universal Method for Network Architecture Transformation,” The Thirty-Third AAAI Conference on Artificial Intelligence (AAAI-19), Jan. 2019.
  7. Hanmin Park, and Kiyoung Choi, “Cell division: weight bit-width reduction technique for convolutional neural network hardware accelerators.” Proceedings of the 24th Asia and South Pacific Design Automation Conference (ASP-DAC). ACM, Jan. 2019.
  8. Hossein Moradian, Sujeong Jo, and Kiyoung Choi, “Reconfigurable Multi-Input Adder Design for Deep Neural Network Accelerators,” International SoC Design Conference, Nov. 2018.
  9. Jaehyun Kim, Chaeun Lee, and Kiyoung Choi, “Energy Efficient Analog Synapse/Neuron Circuit for Binarized Neural Networks,” International SoC Design Conference, Nov. 2018.
  10. Sungbum Kang, Joonsang Yu, and Kiyoung Choi, “Tapered-Ratio Compression for Residual Network,” International SoC Design Conference, Nov. 2018.
  11. Heesu Kim, Euntae Choi, and Kiyoung Choi, “Speaker Verification Based on Deep Neural Network for Text-Constrained Short Commands,” Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, Nov. 2018.
  12. Sujeong Jo, Hanmin Park, Gunhee Lee, and Kiyoung Choi, “Training Neural Networks with Low Precision Dynamic Fixed-Point,” International Conference on Computer Design, pp. 405-408, Oct. 2018.
  13. Dongwoo Lee, Sungbum Kang, and Kiyoung Choi, “ComPEND: Computation Pruning through Early Negative Detection for ReLU in a deep neural network accelerator,”International Conference on Supercomputing, pp. 1-10, Jun. 2018.
  14. Barend Harris, Mansureh S Moghaddam, Duseok Kang, Inpyo Bae, Euiseok Kim, Hyemi Min, Hansu Cho, Sukjin Kim, Bernhard Egger, Soonhoi Ha, and Kiyoung Choi, “Architectures and algorithms for user customization of CNNs,” Asia and South Pacific Design Automation Conference, pp. 540-547, Jan. 2018.
  15. Daewoo Kim, Mansureh S. Moghaddam, Hossein Moradian, Hyeonuk Sim, Jongeun Lee and Kiyoung Choi, “FPGA Implementation of Convolutional Neural Network Based on Stochastic Computing,” International Conference on Field-Programmable Technology, pp. 287-290, Dec. 2017.
  16. Subin Huh, Joonsang Yu, and Kiyoung Choi, “A New Stochastic Mutiplier for Deep Neural Networks, ” International SoC Design Conference, pp. 46-47, Nov. 2017.
  17. Joonsang Yu, Kyounghoon Kim, Jongeun Lee, and Kiyoung Choi, “Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks,” International Conference on Computer Design, pp. 105-112, Nov. 2017.
  18. Mansureh S. Moghaddam, Barend Harris, Duseok Kang, Inpyo Bae, Euiseok Kim, Hyemi Min, Hansu Cho, Sukjin Kim, Bernhard Egger, Soonhoi Ha, and Kiyoung Choi, “Work-in-Progress: Incremental Training of CNNs for User Customization,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp. 1-2, Oct. 2017.
  19. Kyounghoon Kim and Kiyoung Choi, “Synthesis of Multi-variate Stochastic Computing Circuits,” International Conference on Very Large Scale Integration, pp. 1-6, Oct. 2017.
  20. Heesu Kim, Joonsang Yu, and Kiyoung Choi, “Hybrid spiking-stochastic Deep Neural Network, ” International Symposium on VLSI Design, Automation and Test, pp. 1-4, Apr. 2017.
  21. Atul Rahman, Sangyun Oh, Jongeun Lee, and Kiyoung Choi, “Design space exploration of FPGA accelerators for convolutional neural networks,” Design, Automation and Test in Europe, pp. 1147-1152, Mar. 2017.
  22. Bernhard Egger, Hochan Lee, Duseok Kang, Mansureh S. Moghaddam, Youngchul Cho, Yeonbok Lee, Sukjin Kim, Soonhoi Ha, and Kiyoung Choi, “A space- and energy-efficient code compression/decompression technique for coarse-grained reconfigurable architectures,” International Symposium on Code Generation and Optimization, pp. 197-209, Feb. 2017.
  23. Hyeonuk Sim, Dong Nguyen, Jongeun Lee, and Kiyoung Choi, “Scalable stochastic-computing accelerator for convolutional neural networks,” Asia and South Pacific Design Automation Conference, pp. 696-701, Jan. 2017.
  24. Jungwoo Seo, Joonsang Yu, Jongeun Lee and Kiyoung Choi, “A new approach to binarizing neural networks,” International SoC Design Conference, pp. 77-78, Oct. 2016.
  25. Jaehyun Kim, Kiyoung Choi, Sangheon Lee, and Soojung Ryu, “Dynamic clock synchronization scheme between voltage domains in multi-core architecture,” International Conference on Very Large Scale Integration, pp. 1-6, Sep. 2016.
  26. Kyounghoon Kim, Jungki Kim, Joonsang Yu, Jungwoo Seo, Jongeun Lee, and Kiyoung Choi, “Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks,” Design Automation Conference, pp. 124:1-124:6, Jun. 2016.
  27. Jongho Kim, Gunhee Lee, Kiyoung Choi, Yonghwan Kim, Wook Kim, Kyungtae Do, and Jungyun Choi, “Adaptive delay monitoring for wide voltage-range operation,” Design, Automation and Test in Europe, pp. 511-516, Mar. 2016.
  28. Jinho Lee, Jung Ho Ahn, and Kiyoung Choi, “Buffered compares: excavating the hidden parallelism inside DRAM architectures with lightweight logic,” Design, Automation and Test in Europe, pp. 1243-1248, Mar. 2016.
  29. Atul Rahman, Jongeun Lee, and Kiyoung Choi, “Efficient FPGA acceleration of convolutional neural networks using logical-3D compute array,” Design, Automation and Test in Europe, pp. 1393-1398, Mar. 2016.
  30. Kyounghoon Kim, Jongeun Lee, and Kiyoung Choi, “An energy-efficient random number generator for stochastic circuits,” Asia and South Pacific Design Automation Conference, pp. 256-261, Jan. 2016.
  31. Namhyung Kim and Kiyoung Choi, “A design guideline for volatile STT-RAM with ECC and scrubbing,” International SoC Design Conference, pp. 29-30, Nov. 2015.
  32. Kyounghoon Kim, Jongeun Lee, and Kiyoung Choi, “Approximate de-randomizer for stochastic circuits,” International SoC Design Conference, pp. 123-124, Nov. 2015.
  33. Pierre Nicolas-Nicolaz and Kiyoung Choi, “Dynamic error tracking and supply voltage adjustment for low power,” IFIP/IEEE International Conference on Very Large Scale Integration, pp. 74-79, Oct. 2015.
  34. Namhyung Kim, Junwhan Ahn, Woong Seo, and Kiyoung Choi, “Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM,” International Conference on Very Large Scale Integration, pp. 183-188, Oct. 2015.
  35. Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, “A scalable processing-in-memory accelerator for parallel graph processing,” International Symposium on Computer Architecture, pp. 105-117, Jun. 2015.
  36. Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, “PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture,” International Symposium on Computer Architecture, pp. 336-348, Jun. 2015.
  37. Jinho Lee, Junwhan Ahn, Kiyoung Choi, and Kyungsu Kang, “THOR: orchestrated thermal management of cores and networks in 3D many-core architectures,” Asia and South Pacific Design Automation Conference, pp. 773-778, Jan. 2015.
  38. Sungju Han, Jinho Lee, and Kiyoung Choi, “Tree-mesh heterogeneous topology for low-latency NoC,” International Workshop on Network on Chip Architectures, pp. 19-24, Dec. 2014.
  39. Dongwoo Lee and Kiyoung Choi, “Energy-efficient partitioning of hybrid caches in multi-core architecture,” IFIP/IEEE International Conference on Very Large Scale Integration, pp. 37-42, Oct. 2014.
  40. Helin Lin, Kyounghoon Kim, and Kiyoung Choi, “Concept-aware ensemble system for pedestrian detection,” IEEE Intelligent Vehicles Symposium, pp. 140-145, Jun. 2014.
  41. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “Dynamic power management of off-chip links for hybrid memory cubes,” Design Automation Conference, pp. 139:1-139:6, Jun. 2014.
  42. Jae Min Cho and Kiyoung Choi, “An FPGA implementation of high-throughput key-value store using bloom filter,” International Symposium on VLSI Design, Automation and Test, pp. 31-34, Apr. 2014.
  43. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “DASCA: dead write prediction assisted STT-RAM cache architecture,” International Symposium on High Performance Computer Architecture, pp. 25-36, Feb. 2014.
  44. Jihyun Ryoo, Kyuseung Han, and Kiyoung Choi, “Leveraging parallelism in the presence of control flow on CGRAs,” Asia and South Pacific Design Automation Conference, pp. 285-291, Jan. 2014.
  45. Gunhee Lee, Jinho Lee, and Kiyoung Choi, “Towards optimal adaptive routing in 3D NoC with limited vertical bandwidth,” International Workshop on Network on Chip Architectures, pp. 23-26, Dec. 2013.
  46. Hanmin Park and Kiyoung Choi, “General position-based weighted round-robin arbitration for arbitrary traffic patterns,” Workshop on Synthesis And System Integration of Mixed Information Technologies, pp. 44-49, Oct. 2013.
  47. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “Write intensity prediction for energy-efficient non-volatile caches,” International Symposium on Low Power Electronics and Design, pp. 223-228, Sep. 2013.
  48. Jinho Lee and Kiyoung Choi, “A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections,” International Symposium on Networks-on-Chip, pp. 44-45, Apr. 2013.
  49. Hyunjik Song and Kiyoung Choi, “Autonomic diffusive load balancing on many-core architecture using simulated annealing,” International Conference on Autonomic and Autonomous Systems, pp. 90-95, Mar. 2013.
  50. Kyuseung Han, Kiyoung Choi, and Jongeun Lee, “Compiling control-intensive loops for CGRAs with state-based full predication,” Design, Automation and Test in Europe, Mar. 2013.
  51. Manhwee Jo, Kyuseung Han, and Kiyoung Choi, “Enhancing utilization of integer functional units for high-throughput floating point operations on coarse-grained reconfigurable architecture,” International Conference on Green and Human Information Technology, pp. 51-51, Feb. 2013.
  52. Jinho Lee, Dongwoo Lee, Sunwook Kim, and Kiyoung Choi, “Deflection routing in 3D network-on-chip with TSV serialization,” Asia and South Pacific Design Automation Conference, pp. 29-34, Jan. 2013.
  53. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches,” Asia and South Pacific Design Automation Conference, pp. 285-290, Jan. 2013.
  54. Hanmin Park and Kiyoung Choi, “Position-Based weighted round-robin arbitration for equality of service in many-core network-on-chips,” International Workshop on Network on Chip Architectures, pp. 51-56, Dec. 2012.
  55. Dongwoo Lee, Junwhan Ahn, and Kiyoung Choi, “A memetic quantum-inspired evolutionary algorithm for circuit bipartitioning problem,” International SoC Design Conference, pp. 159-162, Nov. 2012.
  56. Mingyang Zhu, Jinho Lee, and Kiyoung Choi, “An adaptive routing algorithm for 3D mesh NoC with limited vertical bandwidth,” IFIP/IEEE International Conference on Very Large Scale Integration, pp. 18-24, Oct. 2012.
  57. Di Wu, Junwhan Ahn, Imyong Lee, and Kiyoung Choi, “Resource-shared custom instruction generation under performance/area constraints,” International Symposium on System-on-Chip, Oct. 2012.
  58. Junwhan Ahn and Kiyoung Choi, “Lower-bits cache for low power STT-RAM caches,” IEEE International Symposium on Circuits and Systems, pp. 480-483, May 2012.
  59. Kyuseung Han, Seongsik Park, and Kiyoung Choi, “State-based full predication for low power coarse-grained reconfigurable architecture,” Design, Automation and Test in Europe, pp. 1367-1372, Mar. 2012.
  60. Jinho Lee and Kiyoung Choi, “Memory-aware mapping and scheduling of tasks and communications on many-core SoC,” Asia and South Pacific Design Automation Conference, pp. 419-424, Jan. 2012.
  61. Jinho Lee, Mingyang Zhu, Kiyoung Choi, Jung Ho Ahn, and Rohit Sharma, “3D network-on-chip with wireless links through inductive coupling,” International SoC Design Conference, pp. 353-356, Nov. 2011.
  62. Yangsu Kim, Kyuseung Han, and Kiyoung Choi, “A host-accelerator communication architecture design for efficient binary acceleration,” International SoC Design Conference, pp. 361-364, Nov. 2011.
  63. Seokhyun Lee and Kiyoung Choi, “High-Level synthesis with distributed controller for fast timing closure,” International Conference on Computer-Aided Design, pp. 193-199, Nov. 2011.
  64. Junwhan Ahn and Kiyoung Choi, “An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors,” International Conference on Hardware/Software Codesign and System Synthesis, pp. 345-353, Oct. 2011.
  65. Rohit Sharma, Tapas Chakravarty, and Kiyoung Choi, “Generalized parameter extraction model for high-speed interconnects with arbitrary boundary conditions,” URSI General Assembly and Scientific Symposium, Aug. 2011.
  66. Kyuseung Han, Seongsik Park, Kiyoung Choi, Jong Kyung Paek, and Jongeun Lee, “Techniques for improving coarse-grained reconfigurable architectures,” IEEE Midwest Symposium on Circuits and Systems, Aug. 2011.
  67. Seongsik Park and Kiyoung Choi, “An approach to code compression for CGRA,” Asia Symposium on Quality Electronic Design, pp. 240-245, Jul. 2011.
  68. Hyunjik Song and Kiyoung Choi, “Simulated annealing-based diffusive load balancing on many-core SoC,” International Conference on Autonomic Computing, pp. 187-188, Jun. 2011.
  69. Jong Kyung Paek, Jongeun Lee, and Kiyoung Choi, “CRM: configurable range memory for fast reconfigurable computing,” Reconfigurable Architectures Workshop, pp. 158-165, May 2011.
  70. Junwhan Ahn, Imyong Lee, and Kiyoung Choi, “A polynomial-time custom instruction identification algorithm based on dynamic programming,” Asia and South Pacific Design Automation Conference, pp. 573-578, Jan. 2011.
  71. Kyuseung Han, Jong Kyung Paek, and Kiyoung Choi, “Acceleration of control flow on CGRA using advanced predicated execution,” International Conference on Field-Programmable Technology, Dec. 2010.
  72. Di Wu, Imyong Lee, and Kiyoung Choi, “Fast custom instruction generation under area constraint,” International SoC Design Conference, pp. 170-172, Nov. 2010.
  73. Rohit Sharma and Kiyoung Choi, “A formal approach toward developing an equivalent circuit for high-speed coupled interconnects with intermediate ground insertion,” Asia Symposium on Quality Electronic Design, pp. 324-331, Jul. 2010.
  74. Jong Kyung Paek, Kiyoung Choi, and Jongeun Lee, “Binary acceleration using coarse-grained reconfigurable architecture,” International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies, pp. 206-211, Jun. 2010.
  75. Ganghee Lee and Kiyoung Choi, “Thermal-aware fault-tolerant system design with coarse-grained reconfigurable array architecture,” NASA/ESA Conference on Adaptive Hardware and Systems, pp. 272-279, Jun. 2010.
  76. Ganghee Lee, Kyungwook Chang, and Kiyoung Choi, “Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable architecture with speculative execution,” Reconfigurable Architectures Workshop, pp. 1-4, Apr. 2010.
  77. Kyungwook Chang and Kiyoung Choi, “Memory-centric communication architecture for reconfigurable computing,” Applied Reconfigurable Computing, pp. 400-405, Mar. 2010.
  78. Ganghee Lee, Seokhyun Lee, Kiyoung Choi, and Nikil D. Dutt, “Routing-aware application mapping considering steiner points for coarse-grained reconfigurable architecture,” Applied Reconfigurable Computing, pp. 231-243, Mar. 2010.
  79. Dongwook Lee, Manhwee Jo, Kyuseung Han, and Kiyoung Choi, “FloRA: coarse-grained reconfigurable Architecture with floating-point operation capability,” International Conference on Field-Programmable Technology, pp. 376-379, Dec. 2009.
  80. Ganghee Lee, Manhwee Jo, Yongjin Ahn, Kiyoung Choi, and Nikil D. Dutt, “QoS-aware dynamic power management for coarse-grained reconfigurable architecture,” International Conference on Field-Programmable Technology, pp. 489-492, Dec. 2009.
  81. Yongho Lee, Kiyoung Choi, and Taewhan Kim, “SAT-based state encoding for peak current minimization,” International SoC Design Conference, pp. 432-435, Nov. 2009.
  82. Hanmin Park, Jong Kyung Paek, Jinho Lee, and Kiyoung Choi, “Leakage power reduction of functional units in processors having zero-overhead loop counter,” International SoC Design Conference, pp. 492-495, Nov. 2009.
  83. Manhwee Jo, Ganghee Lee, Kyungwook Chang, Kyuseung Han, Kiyoung Choi, Hoonmo Yang, and Kiwook Yun, “Coarse-grained reconfigurable architecture for multiple application domains: a case study,” International Conference on Convergence Information Technology, pp. 546-553, Aug. 2009.
  84. Junhee Yoo, Sungjoo Yoo, and Kiyoung Choi, “Multiprocessor system-on-chip designs with active memory processors for higher memory efficiency,” Design Automation Conference, pp. 806-811, Jul. 2009.
  85. Youngchul Cho and Kiyoung Choi, “Code decomposition and recomposition for enhancing embedded software performance,” Asia and South Pacific Design Automation Conference, pp. 624-629, Jan. 2009.
  86. Ganghee Lee, Seokhyun Lee, and Kiyoung Choi, “Automatic mapping of application to coarse-grained reconfigurable architecture based on high-level synthesis techniques,” International SoC Design Conference, pp. 395-398, Nov. 2008.
  87. Manhwee Jo, Dongwook Lee, and Kiyoung Choi, “Chip implementation of a coarse-grained reconfigurable architecture supporting floating-point operations,” International SoC Design Conference, pp. 29-30, Nov. 2008.
  88. Kyungwook Chang and Kiyoung Choi, “Mapping control intensive kernels onto coarse-grained reconfigurable array architecture,” International SoC Design Conference, pp. 362-365, Nov. 2008.
  89. Dong-yeob Shin, Seokhyun Lee, and Kiyoung Choi, “Modeling functional unit delays for bit-level chaining,” International SoC Design Conference, pp. 326-329, Nov. 2008.
  90. HyoukJoong Lee and Kiyoung Choi, “Multi-Codec variable length decoder design with configurable processor,” International SoC Design Conference, pp. 148-151, Nov. 2008.
  91. Jaehyun Baek and Kiyoung Choi, “New address generation scheme for memory-based FFT processor using multiple radix-2 butterflies,” International SoC Design Conference, pp. 273-276, Nov. 2008.
  92. Imyong Lee, Dongwook Lee, and Kiyoung Choi, “ODALRISC: A small, low power, and configurable 32-bit RISC processor,” International SoC Design Conference, pp. 25-26, Nov. 2008.
  93. Dongwook Lee, Sungjoo Yoo, and Kiyoung Choi, “Entry control in network-on-chip for memory power reduction,” International Symposium on Low Power Electronics and Design, pp. 171-176, Aug. 2008.
  94. V. K. Prasad Arava, Manhwee Jo, HyoukJoong Lee, and Kiyoung Choi, “A generic design for encoding and decoding variable length codes in multi-codec video processing engines,” IEEE Computer society Annual Symposium on VLSI, pp. 197-202, Apr. 2008.
  95. Manhwee Jo, V. K. Prasad Arava, Hoonmo Yang, and Kiyoung Choi, “Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture,” IEEE International SoC Conference, pp. 127-130, Sep. 2007.
  96. Youngchul Cho, Nacer-Eddine Zergainoh, Ahmed A. Jerraya, and Kiyoung Choi, “Buffer size reduction through control-flow decomposition,” International Conference on Embedded and Real-Time Computing Systems and Applications, pp. 183-190, Aug. 2007.
  97. Ganghee Lee, Seokhyun Lee, Yongjin Ahn, and Kiyoung Choi, “Automatic bus matrix synthesis based on hardware interface selection for fast communication design space exploration,” Systems, Architectures, MOdeling, and Simulation, pp. 50-57, Jul. 2007.
  98. Imyong Lee, Dongwook Lee, and Kiyoung Choi, “Memory operation inclusive instruction-set extensions and data path generation,” IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pp. 383-390, Jul. 2007.
  99. Youngchul Cho, Nacer-Eddine Zergainoh, Kiyoung Choi, and Ahmed A. Jerraya, “Low runtime-overhead software synthesis for communicating concurrent processes,” International Workshop on Rapid System Prototyping, pp. 195-201, May 2007.
  100. Junhee Yoo, Dongwook Lee, Sungjoo Yoo, and Kiyoung Choi, “Communication architecture synthesis of cascaded bus matrix,” Asia and South Pacific Design Automation Conference, pp. 171-177, Jan. 2007.
  101. Ilhyun Park, Yoonjin Kim, Chulsoo Park, Jeongki Son, Manhwee Jo, and Kiyoung Choi, “Chip implementation of a coarse-grained reconfigurable architecture,” International SoC Design Conference, pp. 628-629, Oct. 2006.
  102. Yoonjin Kim, Ilhyun Park, Kiyoung Choi, and Yunheung Paek, “Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture,” International Symposium on Low Power Electronics and Design, pp. 593-603, Oct. 2006.
  103. Minwook Ahn, Jonghee W. Yoon, Yunheung Paek, Yoonjin Kim, Mary Kiemb, and Kiyoung Choi, “A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures,” Design, Automation and Test in Europe, Mar. 2006.
  104. Junhee Yoo, Xingguang Feng, Kiyoung Choi, Eui-young Chung, and Kyu-Myung Choi, “Worst case execution time analysis for synthesized hardware,” Asia and South Pacific Design Automation Conference, pp. 905-910, Jan. 2006.
  105. Chulsoo Park, Yoonjin Kim, and Kiyoung Choi, “Domain-specific optimization of reconfigurable array architecture,” US-Korea conference, Aug. 2005.
  106. Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung, and Kiyoung Choi, “Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization,” Design, Automation and Test in Europe, pp. 12-17, Mar. 2005.
  107. Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, and Ahmed Amine Jerraya, “Scheduler implementation in MPSoC design,” Asia and South Pacific Design Automation Conference, pp. 151-156, Jan. 2005.
  108. Yoonjin Kim, Chulsoo Park, Shinwon Kang, Hyunjik Song, Jinyong Jung, and Kiyoung Choi, “Design and evaluation of a coarse-grained reconfigurable architecture,” International SoC Design Conference, pp. 227-230, Oct. 2004.
  109. Jongeun Lee, Yoonjin Kim, Jinyong Jung, Shinwon Gang, and Kiyoung Choi, “Reconfigurable ALU array architecture with conditional execution,” International SoC Design Conference, pp. 222-226, Oct. 2004.
  110. Yongjin Ahn, Keesung Han, Youngchul Cho, Junhee Yoo, Jinyong Jung, Ganghee Lee, Kiyoung Choi, Eui-Young Chung, and Kyu-Myung Choi, “An interactive enviornment for SoC design starting from KPN in SystemC,” Global Signal Processing and Expo., Sep. 2004.
  111. Mary Kiemb and Kiyoung Choi, “Memory and architecture exploration with thread shifting for processors in embedded systems,” International Conference on Compilers, Architectures and Synthesis for Embedded Systems, pp. 230-237, Sep. 2004.
  112. Mary Kiemb and Kiyoung Choi, “Application-specific configuration of multithreaded processor architecture for embedded applications,” IEEE International Symposium on Circuits and Systems, May 2004.
  113. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “Energy-efficient instruction set synthesis for application-specific processors,” International Symposium on Low Power Electronics and Design, pp. 330-333, Aug. 2003.
  114. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “An algorithm for mapping loops onto coarse-grained reconfigurable architectures,” ACM Workshop on Languages, Compilers, Tools for Embedded Systems, pp. 183-188, Jun. 2003.
  115. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “Evaluating memory architectures for media applications on coarse-grained reconfigurable architectures,” IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pp. 166-176, Jun. 2003.
  116. Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, and Nacer-Eddine Zergainoh, “Scheduling and timing analysis of HW/SW On-chip communication in MP SoC design,” DATE Conference and Exhibition, pp. 132-137, Mar. 2003.
  117. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “Efficient instruction encoding for automatic instruction set design of configurable ASIPs,” International Conference on Computer-Aided Design, Nov. 2002.
  118. Sunghyun Lee, Sungjoo Yoo, and Kiyoung Choi, “An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model,” International Symposium on Low Power Electronics and Design, pp. 84-87, Aug. 2002.
  119. Sunghyun Lee, Sungjoo Yoo, and Kiyoung Choi, “Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model,” International Symposium on Hardware/Software Codesign, pp. 199-204, May 2002.
  120. Yongjin Ahn, Daehong Kim, Sunghyun Lee, Sanggyu Park, Sungjoo Yoo, Kiyoung Choi, and Soo-Ik Chae, “An efficient simulation environment for the design of networked Bluetooth devices,” Design, Automation and Test in Europe, Mar. 2002.
  121. Daehong Kim, Jinyong Jung, Sunghyun Lee, Jinhwan Jeon, and Kiyoung Choi, “Behavior-to-placed RTL synthesis with performance-driven placement,” International Conference on Computer-Aided Design, Nov. 2001.
  122. Daehong Kim, Dongwan Shin, and Kiyoung Choi, “Low power pipelining of linear systems: A common operand centric apporach,” International Symposium on Low Power Electronics and Design, Aug. 2001.
  123. Kyoungseok Rha and Kiyoung Choi, “Area-efficient buffer binding based on a novel two-port FIFO structure,” International Symposium on Hardware/Software Codesign, pp. 122-127, Apr. 2001.
  124. Seongtaek Lim, Jihong Kim, and Kiyoung Choi, “Scheduling-based code size reduction in processors with indirect addressing mode,” International Symposium on Hardware/Software Codesign, pp. 165-169, Apr. 2001.
  125. Jinyong Jung, Sungjoo Yoo, and Kiyoung Choi, “Performance improvement of multi-processor systems cosimulation based on SW analysis,” DATE Conference and Exhibition, pp. 749-753, Mar. 2001.
  126. Jinhwan Jeon, Daehong Kim, Dongwan Shin, and Kiyoung Choi, “High-level synthesis under multi-cycle interconnect delay,” Asia and South Pacific Design Automation Conference, pp. 662-667, Jan. 2001.
  127. Youngsoo Shin, Kiyoung Choi, and Takayasu Sakurai, “Power optimization of real-time embedded systems on variable speed processors,” International Conference on Computer-Aided Design, pp. 365-368, Nov. 2000.
  128. Jae-Hee Won and Kiyoung Choi, “Low power self-timed floating-point divider in 0.25um technology,” European Solid-State Circuits Conference, Sep. 2000.
  129. Sunghyun Lee, Kiwook Yun, Kiyoung Choi, Seongsoo Hong, Soo-Mook Moon, and Jeonga Lee, “Java-based programmable networked embedded system architecture with multiple application support,” International Conference on Chip Design Automation, pp. 448-451, Aug. 2000.
  130. Jae-Hee Won and Kiyoung Choi, “Low power self-timed radix-2 division,” International Symposium on Low Power Electronics and Design, pp. 210-212, Jul. 2000.
  131. Junghwan Choi, Jinhwan Jeon, and Kiyoung Choi, “Power minimization of functional units by partially guarded computation,” International Symposium on Low Power Electronics and Design, pp. 131-136, Jul. 2000.
  132. Youngsoo Shin, Daehong Kim, and Kiyoung Choi, “Schedulability-driven performance analysis of multiple mode embedded real-time systems,” Design Automation Conference, pp. 495-500, Jun. 2000.
  133. Taekyoon Ahn, Kiyoung Choi, Ki-Hyun Kim, and Seong-Kwan Hong, “A new cost model for high-level power optimization and its application,” IEEE International Symposium on Circuits and Systems, pp. 573-576, May 2000.
  134. Sungjoo Yoo, Kyoungseok Rha, Youngchul Cho, Jinyong Jung, and Kiyoung Choi, “Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model,” International Workshop on Hardware/Software Codesign, pp. 77-81, May 2000.
  135. Sungjoo Yoo, Jongeun Lee, Jinyong Jung, Kyoungseok Rha, Youngchul Cho, and Kiyoung Choi, “Fast hardware-software coverification by optimistic execution of real processor,” DATE Conference and Exhibition, pp. 663-668, Mar. 2000.
  136. Byungil Jeong, Sungjoo Yoo, Sunghyun Lee, and Kiyoung Choi, “Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs,” Asia and South Pacific Design Automation Conference, pp. 169-174, Jan. 2000.
  137. Youngsoo Shin and Kiyoung Choi, “Narrow bus encoding for low power systems,” Asia and South Pacific Design Automation Conference, pp. 217-220, Jan. 2000.
  138. Sanghun Park, Kihun Kim, Hyunseok Chang, Jinhwan Jeon, and Kiyoung Choi, “Backward-annotation of post-layout delay information into high-level synthesis process for performance optimization,” International Conference of VLSI and CAD, pp. 25-28, Oct. 1999.
  139. Sungjoo Yoo, Jongeun Lee, Kyoungseok Rha, Jinyong Jung, Youngchul Cho, and Kiyoung Choi, “Fast prototyping of an IS-95 CDMA cellular phone : a case study,” Asia Pacific Conference on Hardware Description Languages, pp. 61-66, Oct. 1999.
  140. Kisun Kim, Kiyoung Choi, and Young-Hyun Jun, “Hardware synthesis for stack type partitioned-bus architecture,” International Conference on VLSI and CAD, pp. 81-84, Oct. 1999.
  141. Sungjoo Yoo and Kiyoung Choi, “Interleaving partial bus-invert coding for low power reconfiguration of FPGAs,” International Conference on VLSI and CAD, pp. 549-552, Oct. 1999.
  142. Seungryul Lee and Kiyoung Choi, “Partitioned-bus architecture synthesis based on data transfer model,” Asia Pacific Conference on Hardware Description Languages, pp. 144-149, Oct. 1999.
  143. Jae-Hee Won and Kiyoung Choi, “Self-timed statistical carry lookahead adder using multiple-output DCVSL,” International Conference on VLSI and CAD, pp. 560-563, Oct. 1999.
  144. Mary Kiemb and Kiyoung Choi, “Hybrid simulation for IP-based design,” International Workshop on Advanced LSIs - Scaled Device/Process, High Performance Circuits, pp. 27-31, Jul. 1999.
  145. Sanghun Park and Kiyoung Choi, “Performance-driven scheduling with bit-level chaining,” Design Automation Conference, pp. 286-291, Jun. 1999.
  146. Youngsoo Shin and Kiyoung Choi, “Power conscious fixed priority scheduling for hard real-time systems,” Design Automation Conference, pp. 134-139, Jun. 1999.
  147. Sungjoo Yoo and Kiyoung Choi, “Optimizing geographically distributed timed cosimulation by hierarchically grouped messages,” International Workshop on Hardware/Software Codesign, pp. 100-104, May 1999.
  148. Byungil Jeong, Sungjoo Yoo, and Kiyoung Choi, “Exploiting early partial reconfiguration of run-time reconfigurable FPGAs in embedded systems design,” International Symposium on Field Programmable Gate Arrays, pp. 247-247, Feb. 1999.
  149. Youngsoo Shin, Soo-Ik Chae, and Kiyoung Choi, “Partial bus-invert coding for power optimization of system level bus,” International Symposium on Low Power Electronics and Design, pp. 217-129, Aug. 1998.
  150. Youngsoo Shin and Kiyoung Choi, “Rate assignment for embedded reactive real-time systems,” Euromicro Workshop on Digital Systems Design, pp. 237-242, Aug. 1998.
  151. Sanghun Park and Kiyoung Choi, “Sequential circuit optimization by FSM transformation,” Asia Pacific Conference on Hardware Description Languages, pp. 53-58, Jul. 1998.
  152. Hwayong Kim and Kiyoung Choi, “Transformation from C to synthesizable VHDL,” Asia Pacific Conference on Hardware Description Languages, pp. 85-88, Jul. 1998.
  153. Jae-Hee Won and Kiyoung Choi, “Modified half rail differential logic for reduced internal logic swing,” IEEE International Symposium on Circuits and Systems, pp. 157-160, May 1998.
  154. Jinhwan Jeon and Kiyoung Choi, “Loop pipelining in hardware-software partitioning,” Asia and South Pacific Design Automation Conference, pp. 361-366, Feb. 1998.
  155. Sungjoo Yoo and Kiyoung Choi, “Optimistic distributed timed cosimulation based on thread simulation model,” International Workshop on Hardware/Software Codesign, pp. 71-75, 1998.
  156. Taekyoon Ahn and Kiyoung Choi, “Design verification by concurrent simulation and automatic comparison,” IEEE Midwest Symposium on Circuits and Systems, pp. 1087-1090, Aug. 1997.
  157. Dongwan Shin and Kiyoung Choi, “Low power high level synthesis by increasing data correlation,” International Symposium on Low Power Electronics and Design, pp. 62-67, Aug. 1997.
  158. Daehong Kim and Kiyoung Choi, “Power conscious high level synthesis using loop folding,” Design Automation Conference, pp. 441-445, Jun. 1997.
  159. Youngsoo Shin and Kiyoung Choi, “Enhancing schedulability of hard real-time systems through codesign,” IEEE International Symposium on Circuits and Systems, pp. 1576-1579, May 1997.
  160. Taekyoon Ahn and Kiyoung Choi, “VHDL simulation acceleration using specialized functions,” IEEE International Symposium on Circuits and Systems, pp. 1684-1687, May 1997.
  161. Youngsoo Shin and Kiyoung Choi, “Enforcing schedulability of multi-task systems by hardware-software codesign,” International Workshop on Hardware/Software Codesign, Mar. 1997.
  162. Sungjoo Yoo and Kiyoung Choi, “Optmistic timed HW-SW cosimulation,” Asia Pacific Conference on Hardware Description Languages, pp. 39-42, 1997.
  163. Sanghun Park and Kiyoung Choi, “Sequential circuit optimization by FSM trasnformation,” International Workshop on Logic Synthesis, 1997.
  164. Sungjoo Yoo and Kiyoung Choi, “Synchronization overhead reduction in timed cosimulation,” International High Level Design Validation and Test Workshop, pp. 157-164, 1997.
  165. Sungjoo Yoo, Jinhwan Jeon, Seongsoo Hong, and Kiyoung Choi, “Hardware-Software codesign of resource-constrained real-time systems,” International Conference on Real-Time and Embedded Computing Systems and Applications, pp. 286-292, Oct. 1996.
  166. KiJong Lee, Dongwan Shin, and Kiyoung Choi, “A novel self-timed ring structure for SRT division,” International Technical Conference on Circuits Systems, Computers and Communications, pp. 1226-1229, 1996.
  167. Kyuseok Kim, Yongjoo Kim, Youngsoo Shin, and Kiyoung Choi, “An integrated hardware-software cosimulation environment with automated interface generation,” IEEE International Workshop on Rapid System Prototyping, pp. 66-71, 1996.
  168. Taekyoon Ahn and Kiyoung Choi, “Compression of simulation results by sampling,” Asia Pacific Conference on Hardware Description Languages, pp. 155-159, 1996.
  169. Sungjoo Yoo and Kiyoung Choi, “High performance FPGA interconnect delay estimation,” Flat Panel Display Conference, 1996.
  170. Taekyoon Ahn, Koo Hak Kim, Sanghun Park, and Kiyoung Choi, “Incremental analysis and elaboration of VHDL description,” Asia Pacific Conference on Hardware Description Languages, pp. 128-131, 1996.
  171. Youngsoo Shin and Kiyoung Choi, “Software synthesis through task decomposition by dependency analysis,” IEEE International Conference on Universal Personal Communications, pp. 98-102, 1996.
  172. Youngsoo Shin and Kiyoung Choi, “Thread-Based software synthesis for embedded system design,” European Design and Test Conference, pp. 282-286, 1996.
  173. Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, and Soonhoi Ha, “An integrated hardware-software cosimulation environment for heterogeneous systems prototyping,” Asia and South Pacific Design Automation Conference, pp. 101-106, Oct. 1995.
  174. Yongjoo Kim, Youngsoo Shin, Kyuseok Kim, Jae-Hee Won, and Kiyoung Choi, “Efficient prototyping system based on incremental design and module-by-module verification,” IEEE International Symposium on Circuits and Systems, pp. 924-927, May 1995.
  175. Yongjoo Kim, Kyuseok Kim, Daehong Kim, Dae-Hyeop Ko, and Kiyoung Choi, “An efficient VLSI architecture for lempel-ziv-based data compression,” International Conference on VLSI and CAD, pp. 121-124, 1995.
  176. Kiyoung Choi, KiJong Lee, and Jun-Woo Kang, “A self-timed divider using RSD number system,” IEEE International Conference on Computer Design, pp. 504-507, 1994.
  177. Sanghun Park and Kiyoung Choi, “Timing synthesis using timers,” Asia Pacific Conference on Hardware Description Languages, pp. 119-126, 1994.

International Books

  1. Mansureh S. Moghaddam, Jae-Min Cho, and Kiyoung Choi, “Reconfigurable Architectures,” in Handbook of Hardware/Software Codesign, Springer Netherlands, pp. 1–42, Apr. 2017.
  2. Youngsoo Shin, Chi Ying Tsui, Jae-Joon Kim, Kiyoung Choi, and Ricardo Reis, eds., “VLSI-SoC: Design for Reliability, Security, and Low Power,” Springer, Aug. 2016.
  3. Dongwoo Lee and Kiyoung Choi, “Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture,” in VLSI-SoC: Internet of Things Foundations, Springer International Publishing, pp. 58-74, Dec. 2015.
  4. Rohit Sharma and Kiyoung Choi, “Emerging Interconnect Technologies for 3D Networks-on-Chip,” in Design of 3D Integrated Circuits and Systems, Rohit Sharma, eds., CRC Press, pp. 157-174, Nov. 2014.
  5. Kyounghoon Kim and Kiyoung Choi, “SoC Architecture for Automobile Vision System,” in Algorithm & SoC Design for Automotive Vision Systems, Jaeseok Kim and Hyunchul Shin, eds., Springer, pp. 163-195, Sep. 2014.
  6. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “Synthesis of instruction sets for high-performance and energy-efficient ASIP,” in Designing Embedded Processors: A Low Power Perspective, Jörg Henkel and Sri Parameswaran, eds., Springer-Verlag, Jan. 2007.
  7. Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, and Nacer-Eddine Zergainoh, “Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design,” in Embedded Software for SoC, Ahmed Amine Jerraya, Sungjoo Yoo, Diederik Verkest, and Nobert Wehn, eds., Kluwer Academic Publishers, pp. 125-136, Dec. 2003.

International Patents

  1. Sungyeum Kim, Hyeokman Kwon, Youngjun Kwon, Kiyoung Choi, and Junwhan Ahn, “Semiconductor memory device including non-volatile memory, cache memory, and computer system,” UNITED STATES, Samsung Electronics Co., Ltd., 2013-03-08, US 13/790,113, 2016-02-02, US9250997.
  2. Kiyoung Choi, Kyungwook Chang, and Jong Kyung Paek, “Memory-centered communication apparatus in a coarse grained reconfigurable array,” UNITED STATES, 서울대학교 산학협력단, 2012-09-17, 13/635620, 2015-02-03, US 8949550.
  3. Kiwook Yun, V. K. Prasad Arava, Kiyoung Choi, Manhwee Jo, and HyoukJoong Lee, “Variable length decoding apparatus and method,” UNITED STATES, Core Logic, Inc., SNU R&DB Foundation, 2009-12-10, 12/635,558, 2012-01-03, US8089379.
  4. Hoonmo Yang, Manhwee Jo, Ilhyun Park, and Kiyoung Choi, “Reconfigurable paired processing element array configured with context generated each cycle by FSM controller for multi-cycle floating point operation,” UNITED STATES, Core Logic, Inc., 2008-09-19, US 12/234,507, 2011-10-25, US8046564 B2.
  5. Youngsoo Shin, Kiyoung Choi, Byongho Min, and Younghoon Chang, “Bus encoding/decoding apparatus and method,” UNITED STATES, Samsung Electronics Co., Ltd., Kiyoung Choi, 2000-12-28, 09/749,812, 2002-12-03, US6489900.

Domestic Journals

  1. 안준환, 유승주, 최기영, “프로세싱 인 메모리 시스템”, 정보과학회지, vol. 34, no. 7, pp. 15-22, 2016. 7.
  2. 이진호, 최기영, “네트워크 온 칩 기반 매니코어 시스템에서의 매핑 및 라우팅 기법”, 정보과학회지, vol. 32, no. 5, pp. 34-41, 2014. 5.
  3. 류지현, 박한민, 최기영, “GPU를 이용한 quantum-inspired evolutionary algorithm 가속”, 대한전자공학회논문지SD, vol. 49, no. 8, pp. 1-9, 2012. 8.
  4. 안용진, 최기영, “프로세스 네트워크 모델의 정적 분석에 기반을 둔 다중 프로세서 시스템 온 칩 설계 공간 탐색”, 전자공학회논문지, vol. 44, no. 10, pp. 7-16, 2007. 10.
  5. 이성현, 유승주, 최기영, “Hierarchical FSM과 synchronous dataflow model을 이용한 재구성 가능한 SoC의 설계”, 전자공학회논문지, vol. 40, no. 8, pp. 77-88, 2003. 8.
  6. 신영수, 채수익, 최기영, “부분 버스 반전 부호화를 이용한 시스템 수준 전력 최적화”, 전자공학회논문지, vol. 31-C, no. 12, pp. 23-30, 1998.
  7. 김용주, 최기영, “유전자 알고리즘을 이용한 분할 버스 아키텍쳐의 상위 수준 합성”, 전자공학회논문지, vol. 34C, no. 3, pp. 153-162, 1997.
  8. 안태균, 김구학, 박상헌, 최기영, “VHDL 기술의 점진적 분석”, 전자공학회논문지, vol. 34, no. C7, pp. 435-442, 1997.
  9. 신동완, 최기영, “데이타 상관 증가에 의한 저전력 상위 수준 합성”, 전자공학회논문지, vol. 34C, no. 5, pp. 245-252, 1997.
  10. 김대홍, 최기영, “루프의 중첩을 이용한 저전력 상위 수준 합성”, 전자공학회논문지, vol. 34C, no. 6, pp. 347-356, 1997.
  11. 전진환, 최기영, “새로운 시뮬레이티드 어닐링 알고리즘을 이용한 회로 분할 방법”, 전자공학회논문지, vol. 33, no. 9, pp. 223-232, 1996.
  12. 유승주, 최기영, “RC tree의 지연시간 예측”, 전자공학회논문지, vol. 32A, no. 12, pp. 209-219, 1995.
  13. 최승욱, 최기영, “VHDL 설계 데이터베이스 구현 방법의 비교 연구”, 전자공학회논문지, vol. 32B, no. 7, pp. 24-31, 1995.
  14. 김용주, 최기영, “하드웨어-소프트웨어 통합 설계”, CAD 및 VLSI 설계연구회지, vol. 3, no. 2, pp. 73-89, 1994.
  15. 고대협, 최기영, “IVDT: A VHDL Developer’s Toolkit”, KITE Jouranl of Electronics Engineering, vol. 5, no. 2, pp. 56-63, 1994.
  16. 최기영, 강준우, “RSD 수표현 체계를 이용한 셀프타임드 제산기의 구조”, 전자공학회논문지, vol. 31-B, no. 5, pp. 73-80, 1994.
  17. 박상헌, 최기영, “VHDL 표현으로부터의 시간 지연 합성”, 전자공학회논문지, vol. 31-A, no. 6, pp. 209-221, 1994.
  18. 안태균, 최기영, “샘플링에 의한 시뮬레이션 결과의 압축”, 전자공학회논문지, vol. 31- A, no. 5, pp. 158-169, 1994.

Domestic Conferences

  1. 김재현, 이채운, 최기영, “무작위 탐색을 이용한 심층 신경망 학습,” SoC 학술대회, 2019. 05.
  2. 유준상, 강성범, 최기영, “지식 증류법을 활용한 심층 신경망 학습방법 분석”, 대한전자공학회 추계학술대회, pp. 693-696, 2018. 11.
  3. 조수정, 최기영, “동적 고정 소수점을 이용한 신경망 학습에서 비트폭에 따른 정확도 변화”, 대한전자공학회 추계학술대회, pp. 2557-2560, 2017. 11.
  4. 이동우, 최기영, “서포트 벡터 머신 어플리케이션을 활용한 저전압에서 동작하는 매니코어 아키텍처의 평가”, 대한전자공학회 추계학술대회, pp. 31-34, 2016. 11.
  5. 김희수, 최기영, “스파이킹 심층 신경망의 저전력 구현”, 대한전자공학회 추계학술대회, pp. 758-761, 2016. 11.
  6. 이동우, 최기영, “직접 사상 기반 DRAM 캐시를 위한 대역폭 균형 디스패치 기법”, 대한전자공학회 추계학술대회, pp. 60-63, 2015. 11.
  7. 김정기, 최기영, “확률 심층 신경망에서 연산자 정밀도에 대한 연구”, 대한전자공학회 추계학술대회, pp. 687-690, 2015. 11.
  8. Pierre Nicolas-Nicolaz, 최기영, “Adaptive voltage scaling in the near-threshold voltage regime using current sensing completion detection”, 한국반도체학술대회, 2015. 2.
  9. 한성주, 이진호, 최기영, “공유 버스와 팻트리를 이용한 하이브리드 토폴로지 네트워크-온-칩 설계”, 대한전자공학회 추계학술대회, pp. 73-76, 2014. 11.
  10. Pierre Nicolas-Nicolaz, 최기영, “A low overhead flip-N-write method for reducing write energy in STT-RAM caches”, SoC 학술대회, pp. 183-184, 2014. 5.
  11. 박한민, 최기영, “이종 리눅스 클러스터를 이용한 quantum-inspired evolutionary algorithm 가속”, SoC 학술대회, pp. 178-180, 2014. 5.
  12. 김선욱, 이진호, 최기영, “TSV 모델을 포함하는 상위 레벨 3D-IC 열 시뮬레이터”, SoC 학술대회, pp. 164-166, 2014. 5.
  13. 림학림, 박한민, 최기영, “Automatic context funneling을 고려한 GPU 기반 quantum-inspired evolutionary algorithm 가속”, SoC 학술대회, 2013. 5.
  14. 장재훈, 이석현, 최기영, “멀티모드 시스템 설계를 위한 빠른 설계공간 탐색”, 대한전자공학회 추계학술대회, pp. 131-134, 2012. 11.
  15. 류지현, 박한민, 최기영, “GPU를 이용한 quantum-inspired evolutionary algorithm 가속”, SoC 학술대회, 2012. 4.
  16. 주밍양, 이진호, 최기영, “Comparison of two 3D-stacked inductive coupling communication interfaces”, 대한전자공학회 추계학술대회, pp. 35-36, 2011. 11.
  17. 박한민, 최기영, “Quantum-Evolutionary algorithm을 이용한 bit-parallel 가변 길이 복호기의 symbol partitioning 최적화 방법”, 대한전자공학회 추계학술대회, pp. 31-34, 2011. 11.
  18. 김양수, 최기영, “CGRA를 이용한 이진코드내의 자료 의존적 반복문의 가속”, SoC 학술대회, pp. 314-318, 2011. 4.
  19. 박성식, 최기영, “CGRA에서의 효율적인 코드 압축”, SoC 학술대회, pp. 300-304, 2011. 4.
  20. 안준환, 오적, 최기영, 채수익, “LatticeMico32 프로세서를 위한 맞춤 명령어 자동 생성기의 설계”, SoC 학술대회, pp. 145-148, 2011. 4.
  21. 박성식, 한규승, 최기영, “의존도가 있는 반복문을 지원하는 CGRA 구조 제안”, 대한전자공학회 추계학술대회, pp. 30-32, 2010. 11.
  22. 이진호, 최기영, “QEA를 이용한 멀티코어에의 작업할당”, 대한전자공학회 추계학술대회, pp. 12-13, 2010. 11.
  23. 박한민, 김영찬, 최기영, “Zero-Overhead loop 카운터와 drowsy instruction cache를 이용한 저전력 프로세서 설계”, 대한전자공학회 추계학술대회, pp. 67-69, 2010. 11.
  24. 한규승, 유준희, 최기영, “SIMD 기계에서 중첩된 조건문을 위한 조건 실행 방법”, 하계종합학술대회, pp. 656-659, 2010. 6.
  25. 송현직, 최기영, “다중 코어 구조에서 확산적 부하 분산을 통한 쓰레드 매핑 방법”, 하계종합학술대회, pp. 804-807, 2010. 6.
  26. 한승호, 박한민, 최기영, “구성형 프로세서를 이용한 가변 길이 복호 가속”, SoC 학술대회, pp. 394-397, 2010. 4.
  27. 이강희, 이석현, 최기영, “Routing-aware application mapping with integer linear programming for coarse-grained reconfigurable array architecture”, 한국반도체학술대회, pp. 504-505, 2010. 2.
  28. 이석현, 신동엽, 최기영, “Simultaneous allocation, scheduling and binding for high-level synthesis”, 한국반도체학술대회, pp. 412-413, 2010. 2.
  29. 유준희, 최기영, “네트워크-온-칩 구조 생성기의 구현 및 성능 평가”, 대한전자공학회 추계학술대회, 2009. 11.
  30. 조만휘, 이동욱, 한규승, 최기영, “다중 응용프로그램 도메인을 지원하는 재구성 가능 연산 구조의 칩 구현”, 대한전자공학회 추계학술대회, pp. 79-80, 2009. 11.
  31. 유준희, 문영배, 최기영, “네트워크-온-칩을 위한 동적 메모리 관리 방식의 패킷 버퍼”, 대한전자공학회 하계학술대회, pp. 2557-2558, 2009. 7.
  32. 한규승, 최기영, “응용으로부터 재구성형 배열 구조로의 라이브러리 기반 사상”, SoC 학술대회, pp. 64-65, 2009. 5.
  33. 신동엽, 이석현, 최기영, “연산 유닛의 지연시간 - 면적 곡선에 기반을 둔 상위 수준 합성”, SoC 학술대회, pp. 53-54, 2009. 5.
  34. 박한민, 최기영, “Zero-Overhead loop 카운터를 이용한 저전력 프로세서 설계”, 대한전자공학회 추계학술대회, pp. 455-456, 2008. 11.
  35. 이임용, 최기영, “구성형 프로세서의 성능 향상을 위한 pseudo-VLIW 구조”, 대한전자공학회 추계학술대회, pp. 897-898, 2008. 11.
  36. 유준희, 최기영, “네트워크-온-칩 기반의 many-core SoC 설계”, 대한전자공학회 추계학술대회, pp. 891-892, 2008. 11.
  37. 한기성, 장경욱, 최기영, “시스템 비용 절감을 위한 QoS 기반 스케줄링”, 대한전자공학회 추계학술대회, pp. 463-464, 2008. 11.
  38. 이석현, 최기영, “상위 수준 합성에서 loop pipelining과 loop unrolling의 체계적 적용”, SoC 학술대회, pp. 235-238, 2008. 5.
  39. 한규승, 이석현, 이강희, 최기영, “An efficient hardware architecture for intra prediction of h.264 decoder”, 한국반도체학술대회, pp. 124-125, 2008. 2.
  40. 김윤진, 조만휘, 박일현, 최기영, “Chip implementation of power conscious configuration cache for coarse-grained reconfigurable architecture”, 한국반도체학술대회, pp. 527-528, 2008. 2.
  41. 이석현, 안용진, 최기영, “상위수준 합성에서 루프 구문 변환 방법의 개선”, 2007년도 대한전자공학회 소사이어티 추계학술대회, pp. 377-378, 2007. 11.
  42. 송현직, 한기성, 최기영, “SoC 설계 공간 탐색을 위한 소프트웨어 성능의 정적 추정”, 대한전자공학회 전기 전자공학 학술대회 논문집, 2007. 5.
  43. 조만휘, 양훈모, 박일현, 최기영, “부동소수점 연산을 지원하는 재구성 가능 배열 구조”, 대한전자공학회 전기 전자공학 학술대회 논문집, 2007. 5.
  44. 안용진, 최기영, “MPSoC design space exploration based on static analysis of process network model”, 대한전자공학회 전기 전자공학 학술대회 논문집, pp. 7-16, 2007. 1.
  45. 이강희, 안용진, 최기영, “An automatic transaction level code generation for fast SoC design space exploration”, 대한전자공학회 학술회의, 2006. 6.
  46. 정윤경, 이강희, 이석현, 최기영, “트랜잭션 수준 모델링에서의 시뮬레이터 인터페이스 자동생성”, 대한전자공학회 학술회의, 2006. 5.
  47. 문형석, 김선겸, 최기영, “32-bit RISC processor and coprocessor design for AAC”, 한국반도체학술대회, 2006. 2.
  48. 김윤진, 마영란, 최기영, “Efficient design space exploration for domain-specific optimization of coarse-grained reconfigurable architecture”, 대한전자공학회 학술회의, pp. 19-24, 2005. 5.
  49. 김윤진, 정진용, 강신원, 최기영, “재구성형 프로세싱 모듈의 설계”, 대한전자공학회 학술회의, pp. 312-317, 2004. 5.
  50. 이강희, 조영철, 서동관, 최기영, 정의영, “인터페이스 자동생성을 위한 IP 재사용 환경 및 사례 연구”, 대한전자공학회 학술회의, 2004. 5.
  51. 안용진, 한기성, 조영철, 유준희, 정진용, 이강희, 최기영, 정의영, 최규명, “SoC 설계 공간 탐색을 위한 환경 개발”, 대한전자공학회 학술회의, 2004. 5.
  52. 이종은, 최기영, Nikil D. Dutt, “Design space exploration of reconfigurable ALU array (RAA) architectures”, SoC Design Conference, pp. 302-307, 2003. 11.
  53. 류명환, 김대홍, 손희수, 권순민, 최기영, “Interconnect-aware high-level synthesis and module placement for hierarchical FPGA”, SoC Design Conference, pp. 130-135, 2003. 11.
  54. 김선겸, 박영길, 최인찬, 송은석, 최기영, 채수익, “A single-chip, high-speed cycle-accurate energy measurement circuits”, IDEC Conference, pp. 43-46, 2003. 8.
  55. 한기성, 안용진, 이제형, 곽재화, 유준희, 최기영, “자동화 툴을 이용한 HW/SW 분할 및 사례 연구”, CAD 및 VLSI 설계 연구회 학술 발표회 논문집, pp. 131-136, 2003. 5.
  56. 김선겸, 이성현, 최기영, “컴퓨터구조 기술로부터 간단한 RISC 프로세서의 합성”, CAD 및 VLSI 설계 연구회 학술 발표회 논문집, pp. 125-130, 2003. 5.
  57. 소미영, 조영철, 이강희, 서동관, 최기영, “SoC 설계에서 하드웨어 통신 래퍼 자동 생성”, SoC Design Conference, 2002. 10.
  58. 김선겸, 이성현, 최기영, “Synthesis of processor hardware from architecture description”, SoC Design Conference, 2002. 10.
  59. 윤기욱, 김대홍, 최기영, “재구성 가능한 프로세서 구조를 위한 SIMD 기반 확장 명령어의 생성”, SoC Design Conference, pp. 489-495, 2001. 11.
  60. 안용진, 김대홍, 이성현, 박상규, 유승주, 최기영, 채수익, “An efficient simulation environment for the design of networked bluetooth devices”, SoC Design Conference, pp. 622-628, 2001. 11.
  61. 노시정, 장영훈, 김태수, 최기영, “ASIP에서 복잡한 명령어 생성을 위한 하드웨어/소프트웨어 분할”, SoC Design Conference, pp. 327-333, 2001. 11.
  62. 이종은, 최기영, “최적의 명령어집합 설계를 위한 소프트웨어 분석 및 성능예측”, SoC Design Conference, pp. 482-488, 2001. 11.
  63. 조영철, 최기영, “An approach to combining emulation and simulation for efficient debugging of system-on-chip design”, CAD 및 VLSI 설계 연구회 학술 발표회 논문집, pp. 210-214, 2001. 5.
  64. 정진용, 유승주, 최기영, “Performance improvement of multi-processor systems cosimulation based on SW”, CAD 및 VLSI 설계 연구회 학술 발표회 논문집, pp. 159-163, 2001. 5.
  65. 이종은, 조영철, 나경석, 임성택, 정진용, 박수언, 최기영, “내장형 시스템을 위한 통합검증 환경”, CAD 및 VLSI 설계 연구회 학술 발표회 논문집, pp. 194-198, 2001. 5.
  66. 최정환, 전진환, 최기영, “입력 데이터의 부분적 차단을 통한 저전력 기능유닛의 합성”, 한국반도체 학술대회 논문집, pp. 267-268, 2000. 1.
  67. 이성현, 유승주, 최기영, “Java 기반의 재구성 가능한 내장형 시스템 architecture 및 개발환경”, 한국반도체 학술대회 논문집, pp. 495-496, 2000. 1.
  68. 이승열, 최기영, “데이터 전달을 기반으로 하는 분할 버스 구조 합성”, CAD 및 VLSI 설계 연구회 학술 발표회 논문집, pp. 274-279, 1999. 5.
  69. 정병일, 유승주, 최기영, “재구성 가능한 아키텍처를 위한 HW/SW 분할 및 스케줄링”, 한국반도체 학술대회 논문집, pp. 539-540, 1999. 2.
  70. 김형섭, 안태균, 전진환, 김대홍, 최기영, “입력데이터의 상관관계를 고려한 기능 유닛 소비 전력 예측”, 한국반도체 학술대회 논문집, pp. 417-418, 1999. 2.
  71. 김기선, 최기영, “적층 분할 버스 구조를 위한 하드웨어 합성”, 한국반도체 학술대회 논문집, pp. 421-422, 1999. 2.
  72. 안태균, 전영현, 최기영, “Low power filter design by suppressing sign change”, 한국반도체 학술대회 논문집, pp. 399-400, 1999. 2.
  73. 김대홍, 최기영, “저전력 상위 수준 합성을 위한 변환 기법”, 대한전자공학회 학술회의, pp. 1085-1088, 1996. 11.
  74. 신영수, 최기영, “이질적 시스템 설계를 위한 소프트웨어 합성”, CAD 및 VLSI 설계 연구회 학술 발표회 논문집, pp. 70-76, 1996. 1.
  75. 김규석, 최기영, “하드웨어-소프트웨어 통합 설계에서의 인터페이스 모듈생성”, 대한전자공학회 학술회의, pp. 1077-1080, 1995. 12.
  76. 전진환, 최기영, “새로운 시뮬레이티드 어닐링 알고리즘을 이용한 회로 분할 방법”, 대한전자공학회 학술회의, pp. 1089-1092, 1995. 12.
  77. 신영수, 최기영, “내장형 시스템 설계 환경에서의 스레드에 기초한 소프트웨어 합성”, 대한전자공학회 학술회의, pp. 1085-1088, 1995. 1.
  78. 이기종, 최기영, “셀프-타임드 제산기”, 회로 및 시스템 연구회, 전력 전자 연구회 합동 학술발표회 논문집, pp. 94-97, 1994. 1.
  79. 김용주, 신영수, 김규석, 원재희, 최기영, “An efficient computer-aided prototyping system based on FPGAs”, 추계종합학술대회 논문집, pp. 1382-1385, 1994.

Domestic Books

  1. 김재석, 성명준, 신현철, 정윤호, 조경순, 최기영, “시스템 설계 및 근거리 통신용 SoC 설계 기법”, 홍릉과학, 2013. 2.
  2. 김수환, 이혁재, 채수익, 최기영, “논리 설계 및 실험”, 도서출판 그린, 2009. 8.
  3. 최기영, “VHDL의 이해”, 도서출판 기한재, pp. 0-258, 1995.

Domestic Patents

  1. 최기영, 김재현, 이채운, “아날로그 이진인공신경망 회로에서 활성도 조절을 통한 공정변이 보상방법 및 그 시스템”, 한국, 서울대학교 산학협력단, 10-1991041.
  2. 최기영, 이종은, 김경훈, “이진수를 난수로 변환 또는 난수를 이진수로 변환하는 방법 및 그 장치”, 한국, 서울대학교산학협력단, 울산과학기술원, 2016-03-23, 10-2016-0034642, 2017-11-28, 10-1804499.
  3. 최기영, 이진호, 조연곤, 류수정, 정무경, “멀티코어 프로세서에서 수행되는 프로그램의 컴파일 방법, 멀티코어 프로세서의 태스크 매핑 방법 및 태스크 스케줄링 방법”, 한국, (주)삼성전자, 서울대학교산학협력단, 2012-10-11, 10-2012-0113103, 2018-12-03, 10-1926464.
  4. 프라사드, 최기영, 윤기욱, 조만휘, 이혁중, “가변장 복호화 장치 및 방법”, 한국, 서울대학교산학협력단, (주)코아로직, 2009-12-08, 10-2009-0121194, 2012-02-13, 10-1118089-0000.
  5. 양훈모, 조만휘, 박일현, 최기영, “FP-RA를 구성하는 PE 구조 및 그 FP-RA제어하는 FP-RA 제어 회로”, 한국, 서울대학교 산학협력단, (주)코아로직, 2007-09-20, 10-2007-0095852, 2011-12-20, 10-1098758-0000.
  6. 최기영, 장경욱, 백종경, “코어스 그레인 재구성 어레이에서의 메모리 중심 통신장치”, 한국, 서울대학교 산학협력단, 광운대학교 산학협력단, 2010-03-16, , 2011-10-19, 2010-0023414.
  7. 최기영, 유준희, 유승주, 신현철, “능동 메모리 프로세서를 포함하는 네트워크-온-칩 시스템”, 한국, 한양대학교 산학협력단, 서울대학교 산학협력단, 2000-00-00, 1010397820000, 2011-06-01.
  8. 최기영, 이임용, “구성형 프로세서에서 RISC 명령어와 확장 명령어를 병렬 처리하기 위한 방법 및 그에 따른 구성형 프로세서”, 한국, 광운대학교 산학협력단, 서울대학교 산학협력단, 2009-05-29, 10-2009-0047752, 2011-04-26, 1010327710000.
  9. 최기영, 한규승, 백종경, “프로세싱 요소를 통해 명령어를 처리하는 방법 및 프로세싱 장치”, 한국, 서울대학교 산학협력단, 2011-01-14, 10-2011-0004094, 2011-01-01.
  10. 최기영, 한규승, “프로세싱 장치 및 프로세싱 요소제어 장치 및 방법”, 한국, 서울대학교 산학협력단, 광운대학교 산학협력단, 2010-09-01, 10-2010-0085492, 2010-09-01.
  11. 최기영, 프라사드, 윤기욱, 이혁중, 조만휘, “가변장 부호 테이블 분할 방법 및 이를 이용한 멀티 코덱의 메모리 공유 방법 및 장치”, 한국, 서울대학교 산학협력단, (주)코아로직, 2008-10-07, 10-2008-0098324, 2010-06-30, 1009683730000.
  12. 최기영, 장경욱, 백종경, “코어스 그레인 재구성 어레이에서의 메모리 중심 통신 장치”, 한국, 서울대학교 산학협력단, 광운대학교 산학협력단, 2010-03-16, 10-2010-0023414, 2010-03-01.
  13. 양훈모, 조만휘, 박일현, 최기영, “부동 소수점 연산을 지원하는 부동 소수점 유닛-프로세싱 요소(FPU-PE) 구조 및 그 FPU-PE 구조를 포함한 재구성 어레이 프로세서(RAP) 및 그 RAP를 포함한 멀티미디어 플랫폼”, 한국, 서울대학교 산학협력단, (주)코아로직, 2008-09-11, 10-2008-0090012, 2010-03-19, 10-0948512-0000.
  14. 유준희, 이동욱, 최기영, “캐스캐이드 버스 매트릭스를 갖는 통신 구조 합성 방법 및 그 시스템”, 한국, 서울대학교 산학협력단, 2008-02-20, 08-15539, 2009-10-21.
  15. 김윤진, 박일현, 최기영, 백윤흥, “저전력형 컨피규레이션 캐시와 이를 포함하는 재구성형프로세싱 시스템”, 한국, 재단법인서울대학교산학협력재단, 2009-04-02, 10-0863080-0000, 2008-10-02.
  16. 최기영, 정진용, 이종은, 김윤진, 강신원, “조건실행을 지원하는 재구성 가능한 프로세싱 요소의 배열구조”, 한국, 재단법인서울대학교산학협력재단, 2005-01-31, 2005–0008689, 2007-05-22, 10-0722770.
  17. 최기영, 정진용, 마영란, 김윤진, 박철수, “리소스 공유 및 파이프라이닝 구성을 갖는 재구성가능 배열구조”, 한국, 재단법인서울대학교산학협력재단, 2005-02-07, 2005-0011451, 2007-05-21, 10-0722428.
  18. 최기영, 신영수, 민병호, 장영훈, “버스 인코딩/디코딩 장치 및 그 방법”, 한국, 삼성전자주식회사, 최기영, 1999-12-30, 10-1999-0066030, 2004-05-31, 10-0435215-0000.
  19. 김현철, 최기영, 유승주, 이종은, 정진용, 나경석, 조영철, “실제 프로세서를 이용한 낙관적 실행에 의한 하드웨어-소프트웨어 통합 검증방법”, 한국, 한국 MDS (주), 2000-01-18, 2000-002175, 2003-01-06, 368546.
  20. 김용주, 박인학, 최기영, “상위 수준 합성을 위한 트윈 래치를 갖는 분할 버스 구조”, 한국, 김용주, 1997-08-30, 1997-043553, 1999-11-15, 243114.