Publications by Sanghun Park
International Journals
- Sanghun Park and Kiyoung Choi, “Performance-driven high-level synthesis with bit-level chaining and clock selection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, Feb. 2001.
- Sanghun Park and Kiyoung Choi, “Latency minimisation by system clock optimisation,” Electronics Letters, vol. 34, no. 9, pp. 862-864, Jan. 1998.
International Conferences
- Sanghun Park, Kihun Kim, Hyunseok Chang, Jinhwan Jeon, and Kiyoung Choi, “Backward-annotation of post-layout delay information into high-level synthesis process for performance optimization,” International Conference of VLSI and CAD, pp. 25-28, Oct. 1999.
- Sanghun Park and Kiyoung Choi, “Performance-driven scheduling with bit-level chaining,” Design Automation Conference, pp. 286-291, Jun. 1999.
- Sanghun Park and Kiyoung Choi, “Sequential circuit optimization by FSM transformation,” Asia Pacific Conference on Hardware Description Languages, pp. 53-58, Jul. 1998.
- Sanghun Park and Kiyoung Choi, “Sequential circuit optimization by FSM trasnformation,” International Workshop on Logic Synthesis, 1997.
- Taekyoon Ahn, Koo Hak Kim, Sanghun Park, and Kiyoung Choi, “Incremental analysis and elaboration of VHDL description,” Asia Pacific Conference on Hardware Description Languages, pp. 128-131, 1996.
- Sanghun Park and Kiyoung Choi, “Timing synthesis using timers,” Asia Pacific Conference on Hardware Description Languages, pp. 119-126, 1994.
Domestic Journals
- 안태균, 김구학, 박상헌, 최기영, “VHDL 기술의 점진적 분석”, 전자공학회논문지, vol. 34, no. C7, pp. 435-442, 1997.
- 박상헌, 최기영, “VHDL 표현으로부터의 시간 지연 합성”, 전자공학회논문지, vol. 31-A, no. 6, pp. 209-221, 1994.