Publications by Junwhan Ahn

International Journals

  1. Namhyung Kim, Junwhan Ahn, Kiyoung Choi, Daniel Sanchez, Donghoon Yoo, and Soojung Ryu, “Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems,” ACM Transactions on Architecture and Code Optimization, vol. 15, no. 1, pp. 10:1-10:23, Mar. 2018.
  2. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “AIM: Energy-efficient aggregation inside the memory hierarchy,” ACM Transactions on Architecture and Code Optimization, vol. 13, no. 4, pp. 34:1-34:24, Oct. 2016.
  3. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “Prediction hybrid cache: An energy-efficient STT-RAM cache architecture,” IEEE Transactions on Computers, vol. 65, no. 3, pp. 940-951, Mar. 2016.
  4. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “Low-power hybrid memory cubes with link power management and two-level prefetching,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 2, pp. 453-464, Feb. 2016.
  5. Junwhan Ahn and Kiyoung Choi, “LASIC: loop-aware sleepy instruction caches based on STT-RAM technology,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp. 1197-1201, May 2014.
  6. Kyuseung Han, Junwhan Ahn, and Kiyoung Choi, “Power-efficient predication techniques for acceleration of control flow execution on CGRA,” ACM Transactions on Architecture and Code Optimization, vol. 10, no. 2, pp. 8:1-8:25, May 2013.
  7. Junwhan Ahn and Kiyoung Choi, “Isomorphism-aware identification of custom instructions with I/O serialization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 1, pp. 34-46, Jan. 2013.
  8. Di Wu, Imyong Lee, Junwhan Ahn, and Kiyoung Choi, “Fast generation of multiple custom instructions under area constraints,” Journal of Semiconductor Technology and Science, vol. 11, no. 1, pp. 51-58, Mar. 2011.

International Conferences

  1. Namhyung Kim, Junwhan Ahn, Woong Seo, and Kiyoung Choi, “Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM,” International Conference on Very Large Scale Integration, pp. 183-188, Oct. 2015.
  2. Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, “A scalable processing-in-memory accelerator for parallel graph processing,” International Symposium on Computer Architecture, pp. 105-117, Jun. 2015.
  3. Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, “PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture,” International Symposium on Computer Architecture, pp. 336-348, Jun. 2015.
  4. Jinho Lee, Junwhan Ahn, Kiyoung Choi, and Kyungsu Kang, “THOR: orchestrated thermal management of cores and networks in 3D many-core architectures,” Asia and South Pacific Design Automation Conference, pp. 773-778, Jan. 2015.
  5. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “Dynamic power management of off-chip links for hybrid memory cubes,” Design Automation Conference, pp. 139:1-139:6, Jun. 2014.
  6. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “DASCA: dead write prediction assisted STT-RAM cache architecture,” International Symposium on High Performance Computer Architecture, pp. 25-36, Feb. 2014.
  7. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “Write intensity prediction for energy-efficient non-volatile caches,” International Symposium on Low Power Electronics and Design, pp. 223-228, Sep. 2013.
  8. Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi, “Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches,” Asia and South Pacific Design Automation Conference, pp. 285-290, Jan. 2013.
  9. Dongwoo Lee, Junwhan Ahn, and Kiyoung Choi, “A memetic quantum-inspired evolutionary algorithm for circuit bipartitioning problem,” International SoC Design Conference, pp. 159-162, Nov. 2012.
  10. Di Wu, Junwhan Ahn, Imyong Lee, and Kiyoung Choi, “Resource-shared custom instruction generation under performance/area constraints,” International Symposium on System-on-Chip, Oct. 2012.
  11. Junwhan Ahn and Kiyoung Choi, “Lower-bits cache for low power STT-RAM caches,” IEEE International Symposium on Circuits and Systems, pp. 480-483, May 2012.
  12. Junwhan Ahn and Kiyoung Choi, “An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors,” International Conference on Hardware/Software Codesign and System Synthesis, pp. 345-353, Oct. 2011.
  13. Junwhan Ahn, Imyong Lee, and Kiyoung Choi, “A polynomial-time custom instruction identification algorithm based on dynamic programming,” Asia and South Pacific Design Automation Conference, pp. 573-578, Jan. 2011.

International Patents

  1. Sungyeum Kim, Hyeokman Kwon, Youngjun Kwon, Kiyoung Choi, and Junwhan Ahn, “Semiconductor memory device including non-volatile memory, cache memory, and computer system,” UNITED STATES, Samsung Electronics Co., Ltd., 2013-03-08, US 13/790,113, 2016-02-02, US9250997.

Domestic Journals

  1. 안준환, 유승주, 최기영, “프로세싱 인 메모리 시스템”, 정보과학회지, vol. 34, no. 7, pp. 15-22, 2016. 7.

Domestic Conferences

  1. 안준환, 오적, 최기영, 채수익, “LatticeMico32 프로세서를 위한 맞춤 명령어 자동 생성기의 설계”, SoC 학술대회, pp. 145-148, 2011. 4.