Publications by Jinho Lee

International Journals

  1. Jaehyun Kim, Heesu Kim, Subin Huh, Jinho Lee, and Kyoung Choi, “Deep Neural Networks with Weighted Spikes,” Neurocomputing, vol. 311, pp. 373-386, Oct. 2018.
  2. Jinho Lee, Heesu Kim, Sungjoo Yoo, Kiyoung Choi, H. Peter Hofstee, Gi-Joon Nam, Mark R. Nutter, and Damir Jamsek, “ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator,” Proceedings of the VLDB Endowment, vol. 10, no. 12, pp. 1706-1717, Aug. 2017.
  3. Jinho Lee, Jongwook Chung, Jung Ho Ahn, and Kiyoung Choi, “Excavating the hidden parallelism inside DRAM architectures with buffered compares,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 6, pp. 1793-1806, Jun. 2017.
  4. Jinho Lee, Kyungsu Kang, and Kiyoung Choi, “REDELF: An energy-efficient deadlock-free routing for 3D NoCs with partial vertical connections,” ACM Journal on Emerging Technologies in Computing Systems, vol. 12, no. 3, pp. 26:1-26:22, Jan. 2015.
  5. Jinho Lee, Moo-Kyoung Chung, Yeon-Gon Cho, Soojung Ryu, Jung Ho Ahn, and Kiyoung Choi, “Mapping and scheduling of tasks and communications on many-core SoC under local memory constraint,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 11, pp. 1748-1761, Nov. 2013.
  6. Jinho Lee, Dongwoo Lee, Sunwook Kim, and Kiyoung Choi, “Deflection routing in 3D network-on-chip with limited vertical bandwidth,” ACM Transactions on Design Automation of Electronic Systems, vol. 18, no. 4, pp. 50:1-50:22, Oct. 2013.

International Conferences

  1. Jinho Lee, Jung Ho Ahn, and Kiyoung Choi, “Buffered compares: excavating the hidden parallelism inside DRAM architectures with lightweight logic,” Design, Automation and Test in Europe, pp. 1243-1248, Mar. 2016.
  2. Jinho Lee, Junwhan Ahn, Kiyoung Choi, and Kyungsu Kang, “THOR: orchestrated thermal management of cores and networks in 3D many-core architectures,” Asia and South Pacific Design Automation Conference, pp. 773-778, Jan. 2015.
  3. Sungju Han, Jinho Lee, and Kiyoung Choi, “Tree-mesh heterogeneous topology for low-latency NoC,” International Workshop on Network on Chip Architectures, pp. 19-24, Dec. 2014.
  4. Gunhee Lee, Jinho Lee, and Kiyoung Choi, “Towards optimal adaptive routing in 3D NoC with limited vertical bandwidth,” International Workshop on Network on Chip Architectures, pp. 23-26, Dec. 2013.
  5. Jinho Lee and Kiyoung Choi, “A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections,” International Symposium on Networks-on-Chip, pp. 44-45, Apr. 2013.
  6. Jinho Lee, Dongwoo Lee, Sunwook Kim, and Kiyoung Choi, “Deflection routing in 3D network-on-chip with TSV serialization,” Asia and South Pacific Design Automation Conference, pp. 29-34, Jan. 2013.
  7. Mingyang Zhu, Jinho Lee, and Kiyoung Choi, “An adaptive routing algorithm for 3D mesh NoC with limited vertical bandwidth,” IFIP/IEEE International Conference on Very Large Scale Integration, pp. 18-24, Oct. 2012.
  8. Jinho Lee and Kiyoung Choi, “Memory-aware mapping and scheduling of tasks and communications on many-core SoC,” Asia and South Pacific Design Automation Conference, pp. 419-424, Jan. 2012.
  9. Jinho Lee, Mingyang Zhu, Kiyoung Choi, Jung Ho Ahn, and Rohit Sharma, “3D network-on-chip with wireless links through inductive coupling,” International SoC Design Conference, pp. 353-356, Nov. 2011.
  10. Hanmin Park, Jong Kyung Paek, Jinho Lee, and Kiyoung Choi, “Leakage power reduction of functional units in processors having zero-overhead loop counter,” International SoC Design Conference, pp. 492-495, Nov. 2009.

International Patents

  1. Jinho Lee, MooKyoung Chung, Kyuoung Choi, Yeon-gon Cho, Soo-jung Ryu , “Method of compiling program to be executed on multi-core processor, and task mapping method and task scheduling method of reconfigurable processor,” UNITED STATES, Samsung Electronics Co., Ltd., SNU R&DB Foundation, 2013-10-11, US14051910, 2016-03-29, US9298430B2.

Domestic Journals

  1. 이진호, 최기영, “네트워크 온 칩 기반 매니코어 시스템에서의 매핑 및 라우팅 기법”, 정보과학회지, vol. 32, no. 5, pp. 34-41, 2014. 5.

Domestic Conferences

  1. 한성주, 이진호, 최기영, “공유 버스와 팻트리를 이용한 하이브리드 토폴로지 네트워크-온-칩 설계”, 대한전자공학회 추계학술대회, pp. 73-76, 2014. 11.
  2. 김선욱, 이진호, 최기영, “TSV 모델을 포함하는 상위 레벨 3D-IC 열 시뮬레이터”, SoC 학술대회, pp. 164-166, 2014. 5.
  3. 주밍양, 이진호, 최기영, “Comparison of two 3D-stacked inductive coupling communication interfaces”, 대한전자공학회 추계학술대회, pp. 35-36, 2011. 11.
  4. 이진호, 최기영, “QEA를 이용한 멀티코어에의 작업할당”, 대한전자공학회 추계학술대회, pp. 12-13, 2010. 11.

Domestic Patents

  1. 최기영, 이진호, 조연곤, 류수정, 정무경, “멀티코어 프로세서에서 수행되는 프로그램의 컴파일 방법, 멀티코어 프로세서의 태스크 매핑 방법 및 태스크 스케줄링 방법”, 한국, (주)삼성전자, 서울대학교산학협력단, 2012-10-11, 10-2012-0113103, 2018-12-03, 10-1926464.