Publications by Manhwee Jo

International Journals

  1. Manhwee Jo, Dongwook Lee, Kyuseung Han, and Kiyoung Choi, “Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study,” Integration, the VLSI Journal, vol. 47, no. 2, pp. 232-241, Mar. 2014.

International Conferences

  1. Manhwee Jo, Kyuseung Han, and Kiyoung Choi, “Enhancing utilization of integer functional units for high-throughput floating point operations on coarse-grained reconfigurable architecture,” International Conference on Green and Human Information Technology, pp. 51-51, Feb. 2013.
  2. Dongwook Lee, Manhwee Jo, Kyuseung Han, and Kiyoung Choi, “FloRA: coarse-grained reconfigurable Architecture with floating-point operation capability,” International Conference on Field-Programmable Technology, pp. 376-379, Dec. 2009.
  3. Ganghee Lee, Manhwee Jo, Yongjin Ahn, Kiyoung Choi, and Nikil D. Dutt, “QoS-aware dynamic power management for coarse-grained reconfigurable architecture,” International Conference on Field-Programmable Technology, pp. 489-492, Dec. 2009.
  4. Manhwee Jo, Ganghee Lee, Kyungwook Chang, Kyuseung Han, Kiyoung Choi, Hoonmo Yang, and Kiwook Yun, “Coarse-grained reconfigurable architecture for multiple application domains: a case study,” International Conference on Convergence Information Technology, pp. 546-553, Aug. 2009.
  5. Manhwee Jo, Dongwook Lee, and Kiyoung Choi, “Chip implementation of a coarse-grained reconfigurable architecture supporting floating-point operations,” International SoC Design Conference, pp. 29-30, Nov. 2008.
  6. V. K. Prasad Arava, Manhwee Jo, HyoukJoong Lee, and Kiyoung Choi, “A generic design for encoding and decoding variable length codes in multi-codec video processing engines,” IEEE Computer society Annual Symposium on VLSI, pp. 197-202, Apr. 2008.
  7. Manhwee Jo, V. K. Prasad Arava, Hoonmo Yang, and Kiyoung Choi, “Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture,” IEEE International SoC Conference, pp. 127-130, Sep. 2007.
  8. Ilhyun Park, Yoonjin Kim, Chulsoo Park, Jeongki Son, Manhwee Jo, and Kiyoung Choi, “Chip implementation of a coarse-grained reconfigurable architecture,” International SoC Design Conference, pp. 628-629, Oct. 2006.

International Patents

  1. Kiwook Yun, V. K. Prasad Arava, Kiyoung Choi, Manhwee Jo, and HyoukJoong Lee, “Variable length decoding apparatus and method,” UNITED STATES, Core Logic, Inc., SNU R&DB Foundation, 2009-12-10, 12/635,558, 2012-01-03, US8089379.
  2. Hoonmo Yang, Manhwee Jo, Ilhyun Park, and Kiyoung Choi, “Reconfigurable paired processing element array configured with context generated each cycle by FSM controller for multi-cycle floating point operation,” UNITED STATES, Core Logic, Inc., 2008-09-19, US 12/234,507, 2011-10-25, US8046564 B2.

Domestic Conferences

  1. 조만휘, 이동욱, 한규승, 최기영, “다중 응용프로그램 도메인을 지원하는 재구성 가능 연산 구조의 칩 구현”, 대한전자공학회 추계학술대회, pp. 79-80, 2009. 11.
  2. 김윤진, 조만휘, 박일현, 최기영, “Chip implementation of power conscious configuration cache for coarse-grained reconfigurable architecture”, 한국반도체학술대회, pp. 527-528, 2008. 2.
  3. 조만휘, 양훈모, 박일현, 최기영, “부동소수점 연산을 지원하는 재구성 가능 배열 구조”, 대한전자공학회 전기 전자공학 학술대회 논문집, 2007. 5.

Domestic Patents

  1. 프라사드, 최기영, 윤기욱, 조만휘, 이혁중, “가변장 복호화 장치 및 방법”, 한국, 서울대학교산학협력단, (주)코아로직, 2009-12-08, 10-2009-0121194, 2012-02-13, 10-1118089-0000.
  2. 양훈모, 조만휘, 박일현, 최기영, “FP-RA를 구성하는 PE 구조 및 그 FP-RA제어하는 FP-RA 제어 회로”, 한국, 서울대학교 산학협력단, (주)코아로직, 2007-09-20, 10-2007-0095852, 2011-12-20, 10-1098758-0000.
  3. 최기영, 프라사드, 윤기욱, 이혁중, 조만휘, “가변장 부호 테이블 분할 방법 및 이를 이용한 멀티 코덱의 메모리 공유 방법 및 장치”, 한국, 서울대학교 산학협력단, (주)코아로직, 2008-10-07, 10-2008-0098324, 2010-06-30, 1009683730000.
  4. 양훈모, 조만휘, 박일현, 최기영, “부동 소수점 연산을 지원하는 부동 소수점 유닛-프로세싱 요소(FPU-PE) 구조 및 그 FPU-PE 구조를 포함한 재구성 어레이 프로세서(RAP) 및 그 RAP를 포함한 멀티미디어 플랫폼”, 한국, 서울대학교 산학협력단, (주)코아로직, 2008-09-11, 10-2008-0090012, 2010-03-19, 10-0948512-0000.