Publications by Ganghee Lee

International Journals

  1. Kyuseung Han, Ganghee Lee, and Kiyoung Choi, “Software-level approaches for tolerating transient faults in a coarse-grained reconfigurable architecture,” IEEE Transactions on Dependable and Secure Computing, vol. 11, no. 4, pp. 392-398, Jul. 2014.
  2. Ganghee Lee, Kiyoung Choi, and Nikil D. Dutt, “Mapping multi-domain applications onto coarse-grained reconfigurable architectures,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 5, pp. 637-650, May 2011.
  3. Ganghee Lee, Yongjin Ahn, Seokhyun Lee, Jeongki Son, Kiwook Yun, and Kiyoung Choi, “Communication architecture design for reconfigurable multimedia SoC platform,” Design Automation for Embedded Systems, vol. 14, no. 1, pp. 1-20, Mar. 2010.
  4. Yongjin Ahn, Keesung Han, Ganghee Lee, Hyunjik Song, Junhee Yoo, Kiyoung Choi, and Xingguang Feng, “SoCDAL: System-on-Chip Design AcceLerator,” ACM Transactions on Design Automation of Electronic Systems, vol. 17, no. 1, pp. 1-38, Jan. 2008.

International Conferences

  1. Ganghee Lee and Kiyoung Choi, “Thermal-aware fault-tolerant system design with coarse-grained reconfigurable array architecture,” NASA/ESA Conference on Adaptive Hardware and Systems, pp. 272-279, Jun. 2010.
  2. Ganghee Lee, Kyungwook Chang, and Kiyoung Choi, “Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable architecture with speculative execution,” Reconfigurable Architectures Workshop, pp. 1-4, Apr. 2010.
  3. Ganghee Lee, Seokhyun Lee, Kiyoung Choi, and Nikil D. Dutt, “Routing-aware application mapping considering steiner points for coarse-grained reconfigurable architecture,” Applied Reconfigurable Computing, pp. 231-243, Mar. 2010.
  4. Ganghee Lee, Manhwee Jo, Yongjin Ahn, Kiyoung Choi, and Nikil D. Dutt, “QoS-aware dynamic power management for coarse-grained reconfigurable architecture,” International Conference on Field-Programmable Technology, pp. 489-492, Dec. 2009.
  5. Manhwee Jo, Ganghee Lee, Kyungwook Chang, Kyuseung Han, Kiyoung Choi, Hoonmo Yang, and Kiwook Yun, “Coarse-grained reconfigurable architecture for multiple application domains: a case study,” International Conference on Convergence Information Technology, pp. 546-553, Aug. 2009.
  6. Ganghee Lee, Seokhyun Lee, and Kiyoung Choi, “Automatic mapping of application to coarse-grained reconfigurable architecture based on high-level synthesis techniques,” International SoC Design Conference, pp. 395-398, Nov. 2008.
  7. Ganghee Lee, Seokhyun Lee, Yongjin Ahn, and Kiyoung Choi, “Automatic bus matrix synthesis based on hardware interface selection for fast communication design space exploration,” Systems, Architectures, MOdeling, and Simulation, pp. 50-57, Jul. 2007.
  8. Yongjin Ahn, Keesung Han, Youngchul Cho, Junhee Yoo, Jinyong Jung, Ganghee Lee, Kiyoung Choi, Eui-Young Chung, and Kyu-Myung Choi, “An interactive enviornment for SoC design starting from KPN in SystemC,” Global Signal Processing and Expo., Sep. 2004.
  9. Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, and Nacer-Eddine Zergainoh, “Scheduling and timing analysis of HW/SW On-chip communication in MP SoC design,” DATE Conference and Exhibition, pp. 132-137, Mar. 2003.

International Books

  1. Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, and Nacer-Eddine Zergainoh, “Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design,” in Embedded Software for SoC, Ahmed Amine Jerraya, Sungjoo Yoo, Diederik Verkest, and Nobert Wehn, eds., Kluwer Academic Publishers, pp. 125-136, Dec. 2003.

Domestic Conferences

  1. 이강희, 이석현, 최기영, “Routing-aware application mapping with integer linear programming for coarse-grained reconfigurable array architecture”, 한국반도체학술대회, pp. 504-505, 2010. 2.
  2. 한규승, 이석현, 이강희, 최기영, “An efficient hardware architecture for intra prediction of h.264 decoder”, 한국반도체학술대회, pp. 124-125, 2008. 2.
  3. 이강희, 안용진, 최기영, “An automatic transaction level code generation for fast SoC design space exploration”, 대한전자공학회 학술회의, 2006. 6.
  4. 정윤경, 이강희, 이석현, 최기영, “트랜잭션 수준 모델링에서의 시뮬레이터 인터페이스 자동생성”, 대한전자공학회 학술회의, 2006. 5.
  5. 이강희, 조영철, 서동관, 최기영, 정의영, “인터페이스 자동생성을 위한 IP 재사용 환경 및 사례 연구”, 대한전자공학회 학술회의, 2004. 5.
  6. 안용진, 한기성, 조영철, 유준희, 정진용, 이강희, 최기영, 정의영, 최규명, “SoC 설계 공간 탐색을 위한 환경 개발”, 대한전자공학회 학술회의, 2004. 5.
  7. 소미영, 조영철, 이강희, 서동관, 최기영, “SoC 설계에서 하드웨어 통신 래퍼 자동 생성”, SoC Design Conference, 2002. 10.