Publications by Yoonjin Kim

International Journals

  1. Yoonjin Kim, Rabi N. Mahapatra, and Kiyoung Choi, “Design space exploration for efficient resource utilization in coarse-grained reconfigurable architecture,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 10, pp. 1471-1482, Oct. 2010.
  2. Yoonjin Kim, Rabi N. Mahapatra, Ilhyun Park, and Kiyoung Choi, “Low power reconfiguration technique for coarse-grained reconfigurable architecture,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 5, pp. 593-603, May 2009.

International Conferences

  1. Ilhyun Park, Yoonjin Kim, Chulsoo Park, Jeongki Son, Manhwee Jo, and Kiyoung Choi, “Chip implementation of a coarse-grained reconfigurable architecture,” International SoC Design Conference, pp. 628-629, Oct. 2006.
  2. Yoonjin Kim, Ilhyun Park, Kiyoung Choi, and Yunheung Paek, “Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture,” International Symposium on Low Power Electronics and Design, pp. 593-603, Oct. 2006.
  3. Minwook Ahn, Jonghee W. Yoon, Yunheung Paek, Yoonjin Kim, Mary Kiemb, and Kiyoung Choi, “A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures,” Design, Automation and Test in Europe, Mar. 2006.
  4. Chulsoo Park, Yoonjin Kim, and Kiyoung Choi, “Domain-specific optimization of reconfigurable array architecture,” US-Korea conference, Aug. 2005.
  5. Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung, and Kiyoung Choi, “Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization,” Design, Automation and Test in Europe, pp. 12-17, Mar. 2005.
  6. Yoonjin Kim, Chulsoo Park, Shinwon Kang, Hyunjik Song, Jinyong Jung, and Kiyoung Choi, “Design and evaluation of a coarse-grained reconfigurable architecture,” International SoC Design Conference, pp. 227-230, Oct. 2004.
  7. Jongeun Lee, Yoonjin Kim, Jinyong Jung, Shinwon Gang, and Kiyoung Choi, “Reconfigurable ALU array architecture with conditional execution,” International SoC Design Conference, pp. 222-226, Oct. 2004.

Domestic Conferences

  1. 김윤진, 조만휘, 박일현, 최기영, “Chip implementation of power conscious configuration cache for coarse-grained reconfigurable architecture”, 한국반도체학술대회, pp. 527-528, 2008. 2.
  2. 김윤진, 마영란, 최기영, “Efficient design space exploration for domain-specific optimization of coarse-grained reconfigurable architecture”, 대한전자공학회 학술회의, pp. 19-24, 2005. 5.
  3. 김윤진, 정진용, 강신원, 최기영, “재구성형 프로세싱 모듈의 설계”, 대한전자공학회 학술회의, pp. 312-317, 2004. 5.

Domestic Patents

  1. 김윤진, 박일현, 최기영, 백윤흥, “저전력형 컨피규레이션 캐시와 이를 포함하는 재구성형프로세싱 시스템”, 한국, 재단법인서울대학교산학협력재단, 2009-04-02, 10-0863080-0000, 2008-10-02.
  2. 최기영, 정진용, 이종은, 김윤진, 강신원, “조건실행을 지원하는 재구성 가능한 프로세싱 요소의 배열구조”, 한국, 재단법인서울대학교산학협력재단, 2005-01-31, 2005–0008689, 2007-05-22, 10-0722770.
  3. 최기영, 정진용, 마영란, 김윤진, 박철수, “리소스 공유 및 파이프라이닝 구성을 갖는 재구성가능 배열구조”, 한국, 재단법인서울대학교산학협력재단, 2005-02-07, 2005-0011451, 2007-05-21, 10-0722428.