Publications by Youngchul Cho

International Journals

  1. Youngchul Cho and Kiyoung Choi, “Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip,” Design Automation for Embedded Systems, vol. 11, no. 2-3, pp. 167-191, Jul. 2007.

International Conferences

  1. Bernhard Egger, Hochan Lee, Duseok Kang, Mansureh S. Moghaddam, Youngchul Cho, Yeonbok Lee, Sukjin Kim, Soonhoi Ha, and Kiyoung Choi, “A space- and energy-efficient code compression/decompression technique for coarse-grained reconfigurable architectures,” International Symposium on Code Generation and Optimization, pp. 197-209, Feb. 2017.
  2. Youngchul Cho and Kiyoung Choi, “Code decomposition and recomposition for enhancing embedded software performance,” Asia and South Pacific Design Automation Conference, pp. 624-629, Jan. 2009.
  3. Youngchul Cho, Nacer-Eddine Zergainoh, Ahmed A. Jerraya, and Kiyoung Choi, “Buffer size reduction through control-flow decomposition,” International Conference on Embedded and Real-Time Computing Systems and Applications, pp. 183-190, Aug. 2007.
  4. Youngchul Cho, Nacer-Eddine Zergainoh, Kiyoung Choi, and Ahmed A. Jerraya, “Low runtime-overhead software synthesis for communicating concurrent processes,” International Workshop on Rapid System Prototyping, pp. 195-201, May 2007.
  5. Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, and Ahmed Amine Jerraya, “Scheduler implementation in MPSoC design,” Asia and South Pacific Design Automation Conference, pp. 151-156, Jan. 2005.
  6. Yongjin Ahn, Keesung Han, Youngchul Cho, Junhee Yoo, Jinyong Jung, Ganghee Lee, Kiyoung Choi, Eui-Young Chung, and Kyu-Myung Choi, “An interactive enviornment for SoC design starting from KPN in SystemC,” Global Signal Processing and Expo., Sep. 2004.
  7. Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, and Nacer-Eddine Zergainoh, “Scheduling and timing analysis of HW/SW On-chip communication in MP SoC design,” DATE Conference and Exhibition, pp. 132-137, Mar. 2003.
  8. Sungjoo Yoo, Kyoungseok Rha, Youngchul Cho, Jinyong Jung, and Kiyoung Choi, “Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model,” International Workshop on Hardware/Software Codesign, pp. 77-81, May 2000.
  9. Sungjoo Yoo, Jongeun Lee, Jinyong Jung, Kyoungseok Rha, Youngchul Cho, and Kiyoung Choi, “Fast hardware-software coverification by optimistic execution of real processor,” DATE Conference and Exhibition, pp. 663-668, Mar. 2000.
  10. Sungjoo Yoo, Jongeun Lee, Kyoungseok Rha, Jinyong Jung, Youngchul Cho, and Kiyoung Choi, “Fast prototyping of an IS-95 CDMA cellular phone : a case study,” Asia Pacific Conference on Hardware Description Languages, pp. 61-66, Oct. 1999.

International Books

  1. Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, and Nacer-Eddine Zergainoh, “Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design,” in Embedded Software for SoC, Ahmed Amine Jerraya, Sungjoo Yoo, Diederik Verkest, and Nobert Wehn, eds., Kluwer Academic Publishers, pp. 125-136, Dec. 2003.

Domestic Conferences

  1. 이강희, 조영철, 서동관, 최기영, 정의영, “인터페이스 자동생성을 위한 IP 재사용 환경 및 사례 연구”, 대한전자공학회 학술회의, 2004. 5.
  2. 안용진, 한기성, 조영철, 유준희, 정진용, 이강희, 최기영, 정의영, 최규명, “SoC 설계 공간 탐색을 위한 환경 개발”, 대한전자공학회 학술회의, 2004. 5.
  3. 소미영, 조영철, 이강희, 서동관, 최기영, “SoC 설계에서 하드웨어 통신 래퍼 자동 생성”, SoC Design Conference, 2002. 10.
  4. 조영철, 최기영, “An approach to combining emulation and simulation for efficient debugging of system-on-chip design”, CAD 및 VLSI 설계 연구회 학술 발표회 논문집, pp. 210-214, 2001. 5.
  5. 이종은, 조영철, 나경석, 임성택, 정진용, 박수언, 최기영, “내장형 시스템을 위한 통합검증 환경”, CAD 및 VLSI 설계 연구회 학술 발표회 논문집, pp. 194-198, 2001. 5.

Domestic Patents

  1. 김현철, 최기영, 유승주, 이종은, 정진용, 나경석, 조영철, “실제 프로세서를 이용한 낙관적 실행에 의한 하드웨어-소프트웨어 통합 검증방법”, 한국, 한국 MDS (주), 2000-01-18, 2000-002175, 2003-01-06, 368546.