Publications by Seokhyun Lee

International Journals

  1. Seokhyun Lee and Kiyoung Choi, “Critical-path-aware high-level synthesis with distributed controller for fast timing closure,” ACM Transactions on Design Automation of Electronic Systems, vol. 19, no. 2, pp. 16:1-16:29, Mar. 2014.
  2. Ganghee Lee, Yongjin Ahn, Seokhyun Lee, Jeongki Son, Kiwook Yun, and Kiyoung Choi, “Communication architecture design for reconfigurable multimedia SoC platform,” Design Automation for Embedded Systems, vol. 14, no. 1, pp. 1-20, Mar. 2010.

International Conferences

  1. Seokhyun Lee and Kiyoung Choi, “High-Level synthesis with distributed controller for fast timing closure,” International Conference on Computer-Aided Design, pp. 193-199, Nov. 2011.
  2. Ganghee Lee, Seokhyun Lee, Kiyoung Choi, and Nikil D. Dutt, “Routing-aware application mapping considering steiner points for coarse-grained reconfigurable architecture,” Applied Reconfigurable Computing, pp. 231-243, Mar. 2010.
  3. Ganghee Lee, Seokhyun Lee, and Kiyoung Choi, “Automatic mapping of application to coarse-grained reconfigurable architecture based on high-level synthesis techniques,” International SoC Design Conference, pp. 395-398, Nov. 2008.
  4. Dong-yeob Shin, Seokhyun Lee, and Kiyoung Choi, “Modeling functional unit delays for bit-level chaining,” International SoC Design Conference, pp. 326-329, Nov. 2008.
  5. Ganghee Lee, Seokhyun Lee, Yongjin Ahn, and Kiyoung Choi, “Automatic bus matrix synthesis based on hardware interface selection for fast communication design space exploration,” Systems, Architectures, MOdeling, and Simulation, pp. 50-57, Jul. 2007.

Domestic Conferences

  1. 장재훈, 이석현, 최기영, “멀티모드 시스템 설계를 위한 빠른 설계공간 탐색”, 대한전자공학회 추계학술대회, pp. 131-134, 2012. 11.
  2. 이강희, 이석현, 최기영, “Routing-aware application mapping with integer linear programming for coarse-grained reconfigurable array architecture”, 한국반도체학술대회, pp. 504-505, 2010. 2.
  3. 이석현, 신동엽, 최기영, “Simultaneous allocation, scheduling and binding for high-level synthesis”, 한국반도체학술대회, pp. 412-413, 2010. 2.
  4. 신동엽, 이석현, 최기영, “연산 유닛의 지연시간 - 면적 곡선에 기반을 둔 상위 수준 합성”, SoC 학술대회, pp. 53-54, 2009. 5.
  5. 이석현, 최기영, “상위 수준 합성에서 loop pipelining과 loop unrolling의 체계적 적용”, SoC 학술대회, pp. 235-238, 2008. 5.
  6. 한규승, 이석현, 이강희, 최기영, “An efficient hardware architecture for intra prediction of h.264 decoder”, 한국반도체학술대회, pp. 124-125, 2008. 2.
  7. 이석현, 안용진, 최기영, “상위수준 합성에서 루프 구문 변환 방법의 개선”, 2007년도 대한전자공학회 소사이어티 추계학술대회, pp. 377-378, 2007. 11.
  8. 정윤경, 이강희, 이석현, 최기영, “트랜잭션 수준 모델링에서의 시뮬레이터 인터페이스 자동생성”, 대한전자공학회 학술회의, 2006. 5.