Publications by Chaeun Lee
International Conferences
- Chaeun Lee, Jaehyun Kim, and Kiyoung Choi, “An RRAM-based Analog Neuron Design for the Weighted Spiking Neural Netwworks,” International SoC Design Conference, Oct. 2019 (accepted).
- Chaeun Lee, Jaehyun Kim, Jihun Kim, Jaehyun Kim, and Kiyoung Choi, “Fast Simulation Method for Analog Deep Binarized Neural Networks,” International SoC Design Conference, Oct. 2019 (accepted).
- Jaehyun Kim†, Chaeun Lee†, Jihun Kim, Yumin Kim, and Kiyoung Choi, “VCAM: Variation Compensation through Activation Matching for Analog Binarized Neural Networks,” International Symposium on Low Power Electronics and Design, July, 2019 († indicates equal contribution).
- Jaehyun Kim, Chaeun Lee, and Kiyoung Choi, “Energy Efficient Analog Synapse/Neuron Circuit for Binarized Neural Networks,” International SoC Design Conference, Nov. 2018.
Domestic Conferences
- 김재현, 이채운, 최기영, “무작위 탐색을 이용한 심층 신경망 학습,” SoC 학술대회, 2019. 05.
Domestic Patents
- 최기영, 김재현, 이채운, “아날로그 이진인공신경망 회로에서 활성도 조절을 통한 공정변이 보상방법 및 그 시스템”, 한국, 서울대학교 산학협력단, 10-1991041.