---------------------------------------------------------------
-- VHDL code generated by 'cdfg2vhdl'
--
-- Date: Wed Sep 24 18:22:33 1997
-- User: kum
---------------------------------------------------------------
entity ELLIPF is
        port   (
                signal INP : in REAL;
                signal OUTP : out REAL
                --signal SV2 : in REAL;
                --signal SV13 : in REAL;
                --signal SV18 : in REAL;
                --signal SV26 : in REAL;
                --signal SV33 : in REAL;
                --signal SV38 : in REAL;
                --signal SV39 : in REAL;
                --signal SV2_O : out REAL;
                --signal SV13_O : out REAL;
                --signal SV18_O : out REAL;
                --signal SV26_O : out REAL;
                --signal SV33_O : out REAL;
                --signal SV38_O : out REAL;
                --signal SV39_O : out REAL
        );
end ELLIPF;

architecture ELLIPF of ELLIPF is
begin
        mod_1: process (INP)
                variable N1 : REAL;
                variable N2 : REAL;
                variable N3 : REAL;
                variable N4 : REAL;
                variable N5 : REAL;
                variable N6 : REAL;
                variable N7 : REAL;
                variable N8 : REAL;
                variable N9 : REAL;
                variable N10 : REAL;
                variable N11 : REAL;
                variable N12 : REAL;
                variable N13 : REAL;
                variable N14 : REAL;
                variable N15 : REAL;
                variable N16 : REAL;
                variable N17 : REAL;
                variable N18 : REAL;
                variable N19 : REAL;
                variable N20 : REAL;
                variable N21 : REAL;
                variable N22 : REAL;
                variable N23 : REAL;
                variable N24 : REAL;
                variable N25 : REAL;
                variable N26 : REAL;
                variable N27 : REAL;
                variable N28 : REAL;
                variable N29 : REAL;
                variable SV2 : REAL;
                variable SV13 : REAL;
                variable SV18 : REAL;
                variable SV26 : REAL;
                variable SV33 : REAL;
                variable SV38 : REAL;
                variable SV39 : REAL;
        begin
                N1 := INP + SV2;
                N2 := SV33 + SV39;
                N3 := N1 + SV13;
                N4 := N3 + SV26;
                N5 := N4 + N2;
                N6 := (-0.375) * N5;
                N7 := (-0.5) * N5;
                N8 := N3 + N6;
                N9 := N7 + N2;
                N10 := N3 + N8;
                N11 := N8 + N5;
                N12 := N2 + N9;
                N13 := (-0.25) * N10;
                N14 := (-0.53125) * N12;
                N15 := N1 + N13;
                N16 := N14 + SV39;
                N17 := N1 + N15;
                N18 := N15 + N8;
                N19 := N9 + N16;
                N20 := N16 + SV39;
                N21 := (-0.5) * N17;
                N22 := N18 + SV18;
                N23 := SV38 + N19;
                N24 := 0.71875 * N20;
                N25 := INP + N21;
                N26 := 0.5 * N22;
                N27 := 0.875 * N23;
                N28 := N26 - SV18;
                N29 := N27 - SV38;
                SV2 := N25 + N15;
                SV13 := N22 - N28;
                SV18 := N28;
                SV26 := N9 + N11;
                SV38 := N29;
                SV33 := N23 + N29;
                SV39 := N16 - N24;
                OUTP <= N24;
        end process;
end ELLIPF;

configuration CFG_ELLIPF of ELLIPF is
    for ELLIPF
    end for;
end CFG_ELLIPF;

