Publications by Jongeun Lee

International Journals

  1. Aidyn Zhakatayev, Kyounghoon Kim, Kiyoung Choi, and Jongeun Lee, “An efficient and accurate stochastic number generator using even-distribution coding,IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 12, pp. 3056-3066, Dec. 2018.
  2. Jongeun Lee, Seongseok Seo, Jong Kyung Paek, and Kiyoung Choi, “Configurable range memory for effective data reuse on programmable accelerators,” ACM Transactions on Design Automation of Electronic Systems, vol. 19, no. 2, pp. 13:1-13:22, Mar. 2014.
  3. Jong Kyung Paek, Kiyoung Choi, and Jongeun Lee, “Binary acceleration using coarse-grained reconfigurable architecture,” ACM SIGARCH Computer Architecture News, vol. 38, no. 4, pp. 33-39, Sep. 2010.
  4. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “Evaluating memory architectures for media applications on coarse-grained reconfigurable architectures,” International Journal of Embedded Systems, vol. 3, no. 3, pp. 119-127, Oct. 2008.
  5. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “Instruction set synthesis with efficient instruction encoding for configurable processors,” ACM Transactions on Design Automation of Electronic Systems, vol. 12, no. 1, pp. 1-37, Jan. 2007.
  6. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “An algorithm for mapping loops onto coarse-grained reconfigurable architectures,” ACM SIGPLAN Notices, vol. 38, no. 7, pp. 183-188, Jul. 2003.
  7. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “Compilation approach for coarse-grained reconfigurable architectures,” IEEE Design & Test of Computers, vol. 20, no. 1, pp. 26-33, Jan. 2003.

International Conferences

  1. Daewoo Kim, Mansureh S. Moghaddam, Hossein Moradian, Hyeonuk Sim, Jongeun Lee and Kiyoung Choi, “FPGA Implementation of Convolutional Neural Network Based on Stochastic Computing,International Conference on Field-Programmable Technology, pp. 287-290, Dec. 2017.
  2. Joonsang Yu, Kyounghoon Kim, Jongeun Lee, and Kiyoung Choi, “Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks,” International Conference on Computer Design, pp. 105-112, Nov. 2017.
  3. Atul Rahman, Sangyun Oh, Jongeun Lee, and Kiyoung Choi, “Design space exploration of FPGA accelerators for convolutional neural networks,” Design, Automation and Test in Europe, pp. 1147-1152, Mar. 2017.
  4. Hyeonuk Sim, Dong Nguyen, Jongeun Lee, and Kiyoung Choi, “Scalable stochastic-computing accelerator for convolutional neural networks,” Asia and South Pacific Design Automation Conference, pp. 696-701, Jan. 2017.
  5. Jungwoo Seo, Joonsang Yu, Jongeun Lee and Kiyoung Choi, “A new approach to binarizing neural networks,” International SoC Design Conference, pp. 77-78, Oct. 2016.
  6. Kyounghoon Kim, Jungki Kim, Joonsang Yu, Jungwoo Seo, Jongeun Lee, and Kiyoung Choi, “Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks,” Design Automation Conference, pp. 124:1-124:6, Jun. 2016.
  7. Atul Rahman, Jongeun Lee, and Kiyoung Choi, “Efficient FPGA acceleration of convolutional neural networks using logical-3D compute array,” Design, Automation and Test in Europe, pp. 1393-1398, Mar. 2016.
  8. Kyounghoon Kim, Jongeun Lee, and Kiyoung Choi, “An energy-efficient random number generator for stochastic circuits,” Asia and South Pacific Design Automation Conference, pp. 256-261, Jan. 2016.
  9. Kyounghoon Kim, Jongeun Lee, and Kiyoung Choi, “Approximate de-randomizer for stochastic circuits,” International SoC Design Conference, pp. 123-124, Nov. 2015.
  10. Kyuseung Han, Kiyoung Choi, and Jongeun Lee, “Compiling control-intensive loops for CGRAs with state-based full predication,” Design, Automation and Test in Europe, Mar. 2013.
  11. Kyuseung Han, Seongsik Park, Kiyoung Choi, Jong Kyung Paek, and Jongeun Lee, “Techniques for improving coarse-grained reconfigurable architectures,” IEEE Midwest Symposium on Circuits and Systems, Aug. 2011.
  12. Jong Kyung Paek, Jongeun Lee, and Kiyoung Choi, “CRM: configurable range memory for fast reconfigurable computing,” Reconfigurable Architectures Workshop, pp. 158-165, May 2011.
  13. Jong Kyung Paek, Kiyoung Choi, and Jongeun Lee, “Binary acceleration using coarse-grained reconfigurable architecture,” International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies, pp. 206-211, Jun. 2010.
  14. Jongeun Lee, Yoonjin Kim, Jinyong Jung, Shinwon Gang, and Kiyoung Choi, “Reconfigurable ALU array architecture with conditional execution,” International SoC Design Conference, pp. 222-226, Oct. 2004.
  15. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “Energy-efficient instruction set synthesis for application-specific processors,” International Symposium on Low Power Electronics and Design, pp. 330-333, Aug. 2003.
  16. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “An algorithm for mapping loops onto coarse-grained reconfigurable architectures,” ACM Workshop on Languages, Compilers, Tools for Embedded Systems, pp. 183-188, Jun. 2003.
  17. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “Evaluating memory architectures for media applications on coarse-grained reconfigurable architectures,” IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pp. 166-176, Jun. 2003.
  18. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “Efficient instruction encoding for automatic instruction set design of configurable ASIPs,” International Conference on Computer-Aided Design, Nov. 2002.
  19. Sungjoo Yoo, Jongeun Lee, Jinyong Jung, Kyoungseok Rha, Youngchul Cho, and Kiyoung Choi, “Fast hardware-software coverification by optimistic execution of real processor,” DATE Conference and Exhibition, pp. 663-668, Mar. 2000.
  20. Sungjoo Yoo, Jongeun Lee, Kyoungseok Rha, Jinyong Jung, Youngchul Cho, and Kiyoung Choi, “Fast prototyping of an IS-95 CDMA cellular phone : a case study,” Asia Pacific Conference on Hardware Description Languages, pp. 61-66, Oct. 1999.

International Books

  1. Jongeun Lee, Kiyoung Choi, and Nikil D. Dutt, “Synthesis of instruction sets for high-performance and energy-efficient ASIP,” in Designing Embedded Processors: A Low Power Perspective, Jörg Henkel and Sri Parameswaran, eds., Springer-Verlag, Jan. 2007.

Domestic Conferences

  1. 이종은, 최기영, Nikil D. Dutt, “Design space exploration of reconfigurable ALU array (RAA) architectures”, SoC Design Conference, pp. 302-307, 2003. 11.
  2. 이종은, 최기영, “최적의 명령어집합 설계를 위한 소프트웨어 분석 및 성능예측”, SoC Design Conference, pp. 482-488, 2001. 11.
  3. 이종은, 조영철, 나경석, 임성택, 정진용, 박수언, 최기영, “내장형 시스템을 위한 통합검증 환경”, CAD 및 VLSI 설계 연구회 학술 발표회 논문집, pp. 194-198, 2001. 5.

Domestic Patents

  1. 최기영, 이종은, 김경훈, “이진수를 난수로 변환 또는 난수를 이진수로 변환하는 방법 및 그 장치”, 한국, 서울대학교산학협력단, 울산과학기술원, 2016-03-23, 10-2016-0034642, 2017-11-28, 10-1804499.
  2. 최기영, 정진용, 이종은, 김윤진, 강신원, “조건실행을 지원하는 재구성 가능한 프로세싱 요소의 배열구조”, 한국, 재단법인서울대학교산학협력재단, 2005-01-31, 2005–0008689, 2007-05-22, 10-0722770.
  3. 김현철, 최기영, 유승주, 이종은, 정진용, 나경석, 조영철, “실제 프로세서를 이용한 낙관적 실행에 의한 하드웨어-소프트웨어 통합 검증방법”, 한국, 한국 MDS (주), 2000-01-18, 2000-002175, 2003-01-06, 368546.